Datasheet

DP83630

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SNLS335B –OCTOBER 2010–REVISED APRIL 2013

Table 6-2. Supported SCMII Packet Sizes at +/-50 ppm Frequency Accuracy

Latency Tolerance Recommended Packet Size at +/- 50 ppm

Start Threshold RBR[1:0]

100 Mb 10 Mb 100 Mb 10 Mb

01 (default) 4 bits 8 bits 4,000 bytes 9,600 bytes

10 4 bits 8 bits 4,000 bytes 9,600 bytes

11 8 bits 8 bits 9,600 bytes 9,600 bytes

00 8 bits 8 bits 9,600 bytes 9,600 bytes

6.4 IEEE 802.3u MII SERIAL MANAGEMENT INTERFACE

6.4.1 Serial Management Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that

are accessible through the management interface pins MDC and MDIO. The DP83630 implements all the

required MII registers as well as several optional registers. These registers are fully described in Register

Block. A description of the serial management access protocol follows.

6.4.2 Serial Management Access Protocol

The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data

Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is

bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 6-

Table 6-3. Typical MDIO Frame Format

MII Management Serial Protocol <idle><start><opcode><device addr><reg addr><turnaround><data><idle>

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>

Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high.

The DP83630 also includes an option to enable an internal pull-up on the MDIO pin, MDIO_PULL_EN bit

in the CDCTRL1 register. In order to initialize the MDIO interface, the station management entity sends a

sequence of 32 contiguous logic ones on MDIO to provide the DP83630 with a sequence that can be used

to establish synchronization. This preamble may be generated either by driving MDIO high for 32

consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high

during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to

re-sync the device if an invalid Start, Opcode, or turnaround bit is detected.

The DP83630 waits until it has received this preamble sequence before responding to any other

transaction. Once the DP83630 serial management port has been initialized no further preamble

sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround (TA)

bit has occurred.

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