Datasheet

VCC

165:

2.2 k:

165:165:

GND

AN0 = 1AN1 = 1AN_EN = 0

LED_LINK

LED_

SPEED

LED_

ACT

DP83630

www.ti.com

SNLS335B –OCTOBER 2010–REVISED APRIL 2013

Figure 5-2. AN Strapping and LED Loading Example

5.6.2 LED Direct Control

The DP83630 provides another option to directly control any or all LED outputs through the LED Direct

Control Register (LEDCR), address 18h. The register does not provide read access to LEDs.

5.7 HALF DUPLEX vs. FULL DUPLEX

The DP83630 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex

mode, Carrier Sense (CRS) responds to both transmit and receive activity in order to maintain compliance

with the IEEE 802.3 specification.

Since the DP83630 is designed to support simultaneous transmit and receive activity it is capable of

supporting full-duplex switched applications with a throughput of up to 200 Mb/s when operating in either

100BASE-TX or 100BASE-FX. Because the CSMA/CD protocol does not apply to full-duplex operation,

the DP83630 disables its own internal collision sensing and reporting functions and modifies the behavior

of CRS such that it indicates only receive activity. This allows a full-duplex capable MAC to operate

properly.

All modes of operation (100BASE-TX, 100BASE-FX, 10BASE-T) can run either half-duplex or full-duplex.

Additionally, other than CRS and collision reporting, all remaining MII signaling remains the same

regardless of the selected duplex mode.

It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can

interpret and configure to full-duplex operation, parallel detection can not recognize the difference between

full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the

802.3u specification, if a far-end link partner is configured to a forced full-duplex 100BASE-TX ability, the

parallel detection state machine in the partner would be unable to detect the full-duplex capability of the

far-end link partner. This link segment would negotiate to a half-duplex 100BASE-TX configuration (same

scenario for 10 Mb/s).

Auto-Negotiation is not supported in 100BASE-FX operation. Selection of Half or Full-duplex operation is

controlled by bit 8 of the Basic Mode Control Register (BMCR), address 00h. If 100BASE-FX mode is

strapped using the RX_ER pin, the AN0 strap value is used to set the value of bit 8 of the BMCR (00h)

mode.

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Product Folder Links: DP83630