Datasheet

T2.32.1
TX_CLK
X1
DataIDLE Data(J/K) (TR)
T2.31.4
T2.31.1
T2.31.5
T2.31.3
T2.31.2
T2.31.2
PMD Input
Pair
X1
CRS/CSR_DV
RX_DV
RXD[3:0]
RX_ER
DP83630
SNLS335B –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
4.35 AC Specifications — Single Clock MII (SCMII) Receive Timing
Parameter Description Notes Min Typ Max Units
T2.31.1 X1 Clock Period 25 MHz Reference Clock 40 ns
T2.31.2 RXD[3:0], RX_DV and RX_ER output
From X1 rising edge 2 18 ns
delay
(1)
T2.31.3 100BASE-TX mode 19
CRS ON delay
(2)(3)
bits
100BASE-FX mode 9
T2.31.4 100BASE-TX mode 26
CRS OFF delay
(2)(4)
bits
100BASE-FX mode 16
T2.31.5 100BASE-TX mode 56
RXD[3:0] and RX_ER latency
(5)
bits
100BASE-FX mode 46
(1) Output delays assume a 25 pF load.
(2) CRS is asserted and de-asserted asynchronously relative to the reference clock.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
4.36 AC Specifications — 100 Mb/s X1 to TX_CLK Timing
Parameter Description Notes Min Typ Max Units
T2.32.1 X1 to TX_CLK delay
(1)
100 Mb/s Normal mode 0 5 ns
(1) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit MII data.
36 Electrical Specifications Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83630