Datasheet

TX_CLK
TX_EN
TXD[3:0]
CRS/CRS_DV
RX_CLK
RX_DV
RXD[3:0]
T2.22.1
PMD Input
Pair
SD+ internal
T2.21.1 T2.21.2
DP83630
SNLS335B –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
4.25 AC Specifications — 100BASE-TX Signal Detect Timing
Parameter Description Notes Min Typ Max Units
T2.21.1 SD Internal Turn-on Time 1 ms
T2.21.2 Default operation
(1)
250 300 µs
SD Internal Turn-off Time Fast link-loss indication 1.3 µs
enabled
(2)
(1) The signal amplitude on PMD Input Pair must be TP-PMD compliant.
(2) Fast Link-loss detect is enabled by setting the SD_CNFG[8] register bit to a 1.
4.26 AC Specifications — 100 Mb/s Internal Loopback Timing
Parameter Description Notes Min Typ Max Units
T2.22.1 TX_EN to RX_DV Loopback
(1)(2)
100 Mb/s internal loopback mode 240 ns
(1) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during
which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the
initial 550µs “dead-time”.
(2) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
30 Electrical Specifications Copyright © 2010–2013, Texas Instruments Incorporated
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