Datasheet

T2.12.1
T2.12.3T2.12.2
Valid Data
RX_CLK
RXD[3:0]
RX_DV
T2.12.1
T2.11.1 T2.11.1
T2.11.2
T2.11.3
Valid Data
TX_CLK
TXD[3:0]
TX_EN
IDLE(T/R)DATA
T2.10.1
CRS/CRS_DV
PMD Input Pair
DP83630
SNLS335B –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
4.14 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion
Timing
Parameter Description Notes Min Typ Max Units
T2.10.1 100BASE-TX mode 24
Carrier Sense OFF Delay
(1)(2)
bits
100BASE-FX mode 14
(1) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense
(2) 1 bit time = 10 ns in 100 Mb/s mode.
4.15 AC Specifications — 10 Mb/s MII Transmit Timing
Parameter Description Notes Min Typ Max Units
T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
T2.11.2 TXD[3:0], TX_EN Data Setup to
10 Mb/s MII mode 25 ns
TX_CLK falling edge
(1)
T2.11.3 TXD[3:0], TX_EN Data Hold from
10 Mb/s MII mode 0 ns
TX_CLK rising edge
(1) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on
the falling edge of TX_CLK.
4.16 AC Specifications — 10 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T2.12.1 RX_CLK High/Low Time
(1)
160 200 240 ns
T2.12.2 RXD[3:0], RX_DV transition delay from
10 Mb/s MII mode 100 ns
RX_CLK rising edge
T2.12.3 RX_CLK rising edge delay from
10 Mb/s MII mode 100 ns
RXD[3:0], RX_DV valid data
(1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
26 Electrical Specifications Copyright © 2010–2013, Texas Instruments Incorporated
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