Datasheet

Data(J/K)IDLE
T2.9.2
T2.9.1
CRS/CRS_DV
PMD Input Pair
RXD[3:0]
RX_DV
RX_ER
10%
90%
+1 rise
+1 fall
-1 fall
-1 rise
90%
10%
T2.8.1
T2.8.1
T2.8.1
T2.8.1
PMD Output Pair
T2.8.2
PMD Output Pair
eye pattern
T2.8.2
DP83630
www.ti.com SNLS335B –OCTOBER 2010–REVISED APRIL 2013
4.12 AC Specifications — 100BASE-TX Transmit Timing (t
R/F
& Jitter)
Parameter Description Notes Min Typ Max Units
T2.8.1 100 Mb/s PMD Output Pair t
R
and t
F
(1)
3 4 5 ns
100 Mb/s t
R
and t
F
Mismatch
(2)
500 ps
T2.8.2 100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns
(1) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
(2) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
4.13 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Latency
Timing
Parameter Description Notes Min Typ Max Units
T2.9.1 100BASE-TX mode 20
Carrier Sense ON Delay
(1)(2)
bits
100BASE-FX mode 10
T2.9.2 100BASE-TX mode 24
Receive Data Latency
(3)(4)
bits
100BASE-FX mode 14
(1) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100 Mb/s mode.
(3) Enabling IEEE 1588 Receive Timestamp insertion will increase the Receive Data Latency by 40 bit times.
(4) Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive
datapath.
Copyright © 2010–2013, Texas Instruments Incorporated Electrical Specifications 25
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