Datasheet

DP83630
SNLS335B –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
10.7 PTP 1588 CONFIGURATION REGISTERS - PAGE 6
Page 6 PTP 1588 Configuration Registers are accessible by setting bits [2:0] = 110 of PAGESEL (13h).
10.7.1 PTP Clock Output Control Register (PTP_COC), Page 6
This register provides configuration for the PTP clock-synchronized output divide-by-N clock.
Table 10-64. PTP Clock Output Control Register (PTP_COC), address 0x14
Bit Bit Name Default Description
15 PTP_CLKOUT EN 1, RW PTP Clock Output Enable:
1 = Enable PTP divide-by-N clock output.
0 = Disable PTP divide-by-N clock output.
14 PTP_CLKOUT SEL 0, RW PTP Clock Output Source Select:
1 = Select the Phase Generation Module (PGM) as the root clock for generating the
divide-by-N output.
0 = Select the Frequency-Controlled Oscillator (FCO) as the root clock for
generating the divide-by-N output.
For additional information related to the PTP clock output selection, refer to TI Lit
Number SNLA099.
13 PTP_CLKOUT 0, RW PTP Clock Output I/O Speed Select:
SPEEDSEL 1 = Enable faster rise/fall time for the divide-by-N clock output pin.
0 = Enable normal rise/fall time for the divide-by-N clock output pin.
12:8 RESERVED 0 0000, RO Reserved: Writes ignored, Read as 0
7:0 PTP_CLKDIV 0000 1010, RW PTP Clock Divide-by Value:
This field sets the divide-by value for the output clock. The output clock is divided
from an internal 250 MHz clock. Valid values range from 2 to 255 (0x02 to 0xFF),
giving a nominal output frequency range of 125 MHz down to 980.4 kHz. Divide-by
values of 0 and 1 are not valid and will stop the output clock.
10.7.2 PHY Status Frame Configuration Register 1 (PSF_CFG1), Page 6
This register provides configuration for the PHY Status Frame function. Specifically, the 16-bit value in this
register is used as the first 16-bits of the PTP Header data for the PHY Status Frame.
Table 10-65. PHY Status Frame Configuration Register 1 (PSF_CFG1), address 0x15
Bit Bit Name Default Description
15:12 PTPRESERVED 0000, RW PTP v2 reserved field:
This field contains the reserved 4-bit field (at offset 1) to be sent in status packets
from the PHY to the local MAC using the MII receive data interface.
11:8 VERSIONPTP 0000, RW PTP v2 versionPTP field:
This field contains the versionPTP field to be sent in status packets from the PHY to
the local MAC using the MII receive data interface.
7:4 TRANSPORT- 0000, RW PTP v2 Header transportSpecific field:
SPECIFIC This field contains the MESSAGETYPE field to be sent in status packets from the
PHY to the local MAC using the MII receive data interface.
3:0 MESSAGETYPE 0000, RW PTP v2 messageType field:
This field contains the MESSAGETYPE field to be sent in status packets from the
PHY to the local MAC using the MII receive data interface.
126 Register Block Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83630