Datasheet

DP83630
www.ti.com SNLS335B –OCTOBER 2010–REVISED APRIL 2013
10.6.7 PTP Receive Configuration Register 1 (PTP_RXCFG1), Page 5
This register provides data and mask fields to filter the first byte in a PTP Message. This function will be
disabled if all the mask bits are set to 0.
Table 10-58. PTP Receive Configuration Register 1 (PTP_RXCFG1), address 0x1A
Bit Bit Name Default Description
15:8 BYTE0_MASK 0000 0000, RW Byte0 Data:
Bit mask to be used for matching Byte0 of the Receive PTP Message. A one in any
bit enables matching for the associated data bit. If no matching is required, all bits of
the mask should be set to 0.
7:0 BYTE0_DATA 0000 0000, RW Byte0 Mask:
Data to be used for matching Byte0 of the Receive PTP Message.
10.6.8 PTP Receive Configuration Register 2 (PTP_RXCFG2), Page 5
This register provides for programming an IP address to be used for filtering packets to detect PTP Event
Messages. Since the IPv4 address is 32-bits, to write an IP address, software must write two 16-bit
values. The USER_IP_SEL bit in the PTP_RXCFG0 register selects which octects of the IP address are
accessible through this register. For example, to write an IP address of 224.0.1.129, software should do
the following:
1. Set USER_IP_SEL bit in PTP_RXCFG0 register to 0
2. Write 0xE000 (224.00) to PTP_RXCFG2
3. Set USER_IP_SEL bit in the PTP_RXCFG0 register to 1
4. Write 0x0181 (01.129) to PTP_RXCFG2
Reading this registerwill return the IP address field selected by USER_IP_SEL.
Table 10-59. PTP Receive Configuration Register 2 (PTP_RXCFG2), address 0x1B
Bit Bit Name Default Description
15:0 IP_ADDR_DATA 0000 0000 0000 Receive IP Address Data:
0000, RW 16-bits of the IP Address field to be read or written. The USER_IP_SEL bit in the
PTP_RXCFG0 Register selects the portion of the IP address is to be read or written.
Copyright © 2010–2013, Texas Instruments Incorporated Register Block 123
Submit Documentation Feedback
Product Folder Links: DP83630