Datasheet

DP83630
SNLS335B –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
10.6 PTP 1588 CONFIGURATION REGISTERS - PAGE 5
Page 5 PTP 1588 Configuration Registers are accessible by setting bits [2:0] = 101 of PAGESEL (13h).
10.6.1 PTP Trigger Configuration Register (PTP_TRIG), Page 5
This register provides basic configuration for IEEE 1588 Triggers. To write configuration to a Trigger, set
the TRIG_WR bit along with the TRIG_SEL and other control information. To read configuration from a
Trigger, set the TRIG_SEL encoding to the Trigger desired, and set the TRIG_WR bit to 0. The
subsequent read of the PTP_TRIG register will return the configuration information.
Table 10-52. PTP Trigger Configuration Register (PTP_TRIG), address 0x14
Bit Bit Name Default Description
15 TRIG_PULSE 0, RW Trigger Pulse:
Setting this bit will cause the Trigger to generate a Pulse rather than a single rising
or falling edge.
14 TRIG_PER 0, RW Trigger Periodic:
Setting this bit will cause the Trigger to generate a periodic signal. If this bit is 0, the
Trigger will generate a single Pulse or Edge depending on the Trigger Control
settings.
13 TRIG_IF_LATE 0, RW Trigger-if-late Control:
Setting this bit will allow an immediate Trigger in the event the Trigger is
programmed to a time value which is less than the current time. This provides a
mechanism for generating an immediate trigger or to immediately begin generating a
periodic signal. For a periodic signal, no notification be generated if this bit is set
and a Late Trigger occurs.
12 TRIG_NOTIFY 0, RW Trigger Notification Enable:
Setting this bit will enable Trigger status to be reported on completion of a Trigger or
on an error detection due to late trigger. If Trigger interrupts are enabled, the
notification will also result in an interrupt being generated.
11:8 TRIG_GPIO 0000, RW Trigger GPIO Connection:
Setting this field to a non-zero value will connect the Trigger to the associated GPIO
pin. Valid settings for this field are 1 thru 12.
7 TRIG_TOGGLE 0, RW Trigger Toggle Mode Enable:
Setting this bit will put the trigger into toggle mode. In toggle mode, the initial value
will be ignored and the trigger output will be toggled at the trigger time.
6:4 RESERVED 000, RO Reserved: Writes ignored, Read as 0
3:1 TRIG_CSEL 000, RW Trigger Configuration Select:
This field selects the Trigger for configuration read or write.
0 TRIG_WR 0, RW/SC Trigger Configuration Write:
Setting this bit will generate a Configuration Write to the selected Trigger. This bit
will always read back as 0.
118 Register Block Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83630