Datasheet

DP83630SQ
TOP VIEW
(not to scale)
48-pin LLP Package
DAP = GND
IO_VDD IO_VSS RXD_0 RXD_1 RXD_2 RXD_3 COL RX_ER CRS/CRS_DV RX_DV GPIO9 RX_CLK
GPIO8
IO_CORE_VSS
X1
X2
IO_VDD
MDC
MDIO
RESET_N
LED_LINK
LED_SPEED/FX_SD
LED_ACT
GPIO4
RD-
RD+
CD_VSS
TD-
TD+
ANAVSS
ANA33VDD
VREF
GPIO1 GPIO2 GPIO3
CLK_OUT
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
PWRDOWN/INTN
TCK
TDO
TMS
TRST#
TDI
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
DP83630
www.ti.com SNLS335B –OCTOBER 2010–REVISED APRIL 2013
3.1 Pin Layout
Figure 3-1. Top View
Package Number RHS0048A
Copyright © 2010–2013, Texas Instruments Incorporated Pin Descriptions 11
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