Datasheet

DP83630
SNLS335B –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
Table 10-36. Link Quality Monitor Register (LQMR), address 0x1D (continued)
Bit Bit Name Default Description
2 DAGC_LO_WARN 0, RO/COR DAGC Low Warning:
This bit indicates the DAGC Low Threshold was exceeded. This register bit will be
cleared on read.
1 C1_HI_WARN 0, RO/COR C1 High Warning:
This bit indicates the DEQ C1 High Threshold was exceeded. This register bit will
be cleared on read.
0 C1_LO_WARN 0, RO/COR C1 Low Warning:
This bit indicates the DEQ C1 Low Threshold was exceeded. This register bit will
be cleared on read.
10.4.10 Link Quality Data Register (LQDR), Page 2
This register provides read/write control of thresholds for the 100 Mb Link Quality Monitor function. The
register also provides a mechanism for reading current adapted parameter values. Threshold values may
not be written if the device is powered-down.
Table 10-37. Link Quality Data Register (LQDR), address 0x1E
Bit Bit Name Default Description
15:14 RESERVED 00, RO RESERVED: Writes ignored, read as 0.
13 SAMPLE_PARAM 0, RW Sample DSP Parameter:
Setting this bit to a 1 enables reading of current parameter values and initiates
sampling of the parameter value. The parameter to be read is selected by the
LQ_PARAM_SEL bits.
12 WRITE_LQ_THR 0, RW Write Link Quality Threshold:
Setting this bit will cause a write to the Threshold register selected by
LQ_PARAM_SEL and LQ_THR_SEL. The data written is contained in
LQ_THR_DATA. This bit will always read back as 0.
11:9 LQ_PARAM_SEL 000, RW Link Quality Parameter Select:
This 3-bit field selects the Link Quality Parameter. This field is used for sampling
current parameter values as well as for reads/writes to Threshold values. The
following encodings are available:
000: DEQ_C1
001: DAGC
010: DBLW
011: Frequency Offset
100: Frequency Control
101: Variance most significant bits 31:16
108 Register Block Copyright © 2010–2013, Texas Instruments Incorporated
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