Datasheet

DP83620
SNLS339C –JANUARY 2011–REVISED APRIL 2013 www.ti.com
10.4.9 Link Quality Monitor Register (LQMR), Page 2
This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides
a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an
interrupt will be asserted if enabled in the MISR. Monitor control and status are available in this register,
while the LQDR register controls read/write access to threshold values and current parameter values.
Reading the LQMR register clears warning bits and re-arms the interrupt generation. In addition, this
register provides a mechanism for allowing automatic reset of the 100 Mb link based on the Link Quality
Monitor status.
Table 10-36. Link Quality Monitor Register (LQMR), address 0x1D
Bit Bit Name Default Description
15 LQM_ENABLE 0, RW Link Quality Monitor Enable:
Enables the Link Quality Monitor. The enable is qualified by having a valid 100 Mb
link. In addition, the individual thresholds can be disabled by setting to the
maximum or minimum values.
14 RESTART_ON_FC 0, RW Restart on Frequency Control Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a
Frequency Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the
threshold violation will also result in a drop in Link status.
13 RESTART_ON 0, RW Restart on Frequency Offset Warning:
_FREQ Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a
Frequency Offset Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the
threshold violation will also result in a drop in Link status.
12 RESTART_ON 0, RW Restart on DBLW Warning:
_DBLW Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a DBLW
Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the threshold
violation will also result in a drop in Link status.
11 RESTART_ON 0, RW Restart on DAGC Warning:
_DAGC Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a DAGC
Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the threshold
violation will also result in a drop in Link status.
10 RESTART_ON_C1 0, RW Restart on C1 Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a C1
Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the threshold
violation will also result in a drop in Link status.
9 FC_HI_WARN 0, RO/COR Frequency Control High Warning:
This bit indicates the Frequency Control High Threshold was exceeded. This
register bit will be cleared on read.
8 FC_LO_WARN 0, RO/COR Frequency Control Low Warning:
This bit indicates the Frequency Control Low Threshold was exceeded. This
register bit will be cleared on read.
7 FREQ_HI_WARN 0, RO/COR Frequency Offset High Warning:
This bit indicates the Frequency Offset High Threshold was exceeded. This register
bit will be cleared on read.
6 FREQ_LO_WARN 0, RO/COR Frequency Offset Low Warning:
This bit indicates the Frequency Offset Low Threshold was exceeded. This register
bit will be cleared on read.
5 DBLW_HI_WARN 0, RO/COR DBLW High Warning:
This bit indicates the DBLW High Threshold was exceeded. This register bit will be
cleared on read.
4 DBLW_LO_WARN 0, RO/COR DBLW Low Warning:
This bit indicates the DBLW Low Threshold was exceeded. This register bit will be
cleared on read.
3 DAGC_HI_WARN 0, RO/COR DAGC High Warning:
This bit indicates the DAGC High Threshold was exceeded. This register bit will be
cleared on read.
96 Register Block Copyright © 2011–2013, Texas Instruments Incorporated
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