Datasheet

DP83620
www.ti.com SNLS339C –JANUARY 2011–REVISED APRIL 2013
10.2.2 Receiver Error Counter Register (RECR)
This counter provides information required to implement the “Symbol Error During Carrier” attribute within
the PHY managed object class of Clause 30 of the IEEE 802.3u specification.
Table 10-17. Receiver Error Counter Register (RECR), address 0x15
Bit Bit Name Default Description
15:8 RESERVED 0000 0000, RO RESERVED: Writes ignored, read as 0.
7:0 RXERCNT[7:0] 0000 0000, RO/COR RX_ER Counter:
When a valid carrier is present and there is at least one occurrence of an invalid
data symbol, this 8-bit counter increments for each receive error detected. This
event can increment only once per valid carrier event. If a collision is present, the
attribute will not increment. The counter sticks when it reaches its maximum count.
10.2.3 100 Mb/s PCS Configuration and Status Register (PCSR)
This register contains control and status information for the 100BASE Physical Coding Sublayer.
Table 10-18. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16
Bit Bit Name Default Description
15 AUTO_CROSSOV 0, RW Auto-Crossover in Forced Mode:
ER
1 = Auto-Crossover in Forced Mode Enabled
Allows the device to toggle between MDIX and MDI channels when forced to 10M or
100M mode. This function is mutually exclusive with the Auto-Negotiation Enable bit,
BMCR[12], and with the Auto-MDIX Enable bit, PHYCR[15]. These bits should not
be set when enabling Auto-crossover.
0 = Normal operation
14:12 RESERVED 000, RW RESERVED: Must be 0.
11 FREE_CLK 0, RW Receive Clock:
1 = RX_CLK is free-running.
0 = RX_CLK phase adjusted based on alignment.
10 TQ_EN 0, RW 100 Mb/s True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.
9 SD FORCE PMA 0, RW Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
8 SD_OPTION 1, RW Signal Detect Option:
1 = Default operation. Link will be asserted following detection of valid signal level
and Descrambler Lock. Link will be maintained as long as signal level is valid. A loss
of Descrambler Lock will not cause Link Status to drop.
0 = Modified signal detect algorithm. Link will be asserted following detection of valid
signal level and Descrambler Lock. Link will be maintained as long as signal level is
valid and Descrambler remains locked.
7 DESC_TIME 0, RW Descrambler Timeout:
Increase the descrambler timeout. When set, this allows the device to receive larger
packets (>9k bytes) without loss of synchronization.
1 = 2 ms.
0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).
6 FX_EN Strap, RW FX Fiber Mode Enable:
This bit is set when the FX_EN strap option is selected for the respective port.
Write PHYCR2[9], SOFT_RESET, after enabling or disabling Fiber Mode via register
access to ensure correct configuration.
1 = Enables FX operation.
0 = Disables FX operation.
Copyright © 2011–2013, Texas Instruments Incorporated Register Block 81
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