Datasheet

DP83620

SNLS339C –JANUARY 2011–REVISED APRIL 2013

www.ti.com

Table 10-14. MII Interrupt Status and Event Control Register (MISR), address 0x12 (continued)

Bit Bit Name Default Description

4 SPD_INT_EN 0, RW Enable Interrupt on change of speed status.

3 DUP_INT_EN 0, RW Duplex Interrupt:

Enable Interrupt on change of duplex status.

2 ANC_INT_EN 0, RW Enable Interrupt on auto-negotiation complete event.

1 FHF_INT_EN 0, RW FHF Interrupt:

or Enable Interrupt on False Carrier Counter Register halffull event. This function is

CTR_INT_EN selected if the PHYCR2[8:7] are both 0.

CTR Interrupt:

Enable interrupt on either Receive Error Counter Register half-full event or False

Carrier Counter Register half-full event. This function is selected if either of

PCFCR[7:6] are set.

0 RHF_INT_EN 0, RW RHF Interrupt:

or Enable Interrupt on Receive Error Counter Register halffull event. This function is

PCF_INT_EN selected if the PHYCR2[8:7] are both 0.

PCF Interrupt:

Enable Interrupt on a PHY Control Frame event. This function is selected if either

of PCFCR[7:6] are set.

10.1.13 Page Select Register (PAGESEL)

This register is used to enable access to the Link Diagnostics Registers.

Table 10-15. Page Select Register (PAGESEL), address 0x13

Bit Bit Name Default Description

15:3 RESERVED 0000 0000 0000 0, RESERVED: Writes ignored, read as 0

2:0 PAGE_SEL 000, RW Page_Sel Bits:

Selects between paged registers for address 14h to 1Fh.

0 = Extended Registers Page 0

1 = Test Registers Page 1

2 = Link Diagnostics Registers Page 2

5 = PHY Status Frame Configuration Register Page 5

10.2 EXTENDED REGISTERS - PAGE 0

10.2.1 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU

managed object class of Clause 30 of the IEEE 802.3u specification.

Table 10-16. False Carrier Sense Counter Register (FCSCR), address 0x14

Bit Bit Name Default Description

15:8 RESERVED 0000 0000, RO RESERVED: Writes ignored, read as 0

7:0 FCSCNT[7:0] 0000 0000, RO/COR False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This counter sticks when

it reaches its maximum count (FFh).

Submit Documentation Feedback

Product Folder Links: DP83620