Datasheet

DP83620
SNLS339C –JANUARY 2011–REVISED APRIL 2013 www.ti.com
Table 10-12. PHY Status Register (PHYSTS), address 0x10 (continued)
Bit Bit Name Default Description
2 DUPLEX STATUS 0, RO Duplex:
This bit indicates duplex status and is determined from Auto-Negotiation or
Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
1 SPEED STATUS 0, RO Speed10:
This bit indicates the status of the speed and is determined from Auto-
Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
0 LINK STATUS 0, RO Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register, except that it
will not be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
10.1.11 MII Interrupt Control Register (MICR)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation
include: Link Quality Monitor, Energy Detect State Change, Link State Change, Speed Status Change,
Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full. The
individual interrupt events must be enabled by setting bits in the MII Interrupt Status and Event Control
Register (MISR).
Table 10-13. MII Interrupt Control Register (MICR), address 0x11
Bit Bit Name Default Description
15:3 RESERVED 0000 0000 0000 0, RESERVED: Writes ignored, read as 0.
RO
2 TINT 0, RW Test Interrupt:
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will
continue to be generated as long as this bit remains set.
1 = Generate an interrupt.
0 = Do not generate interrupt.
1 INTEN 0, RW Interrupt Enable:
Enable interrupt dependent on the event enables in the MISR register.
1 = Enable event based interrupts.
0 = Disable event based interrupts.
0 INT_OE 0, RW Interrupt Output Enable:
Enable interrupt events to signal via the PWRDOWN/INTN pin by configuring the
PWRDOWN/INTN pin as an output.
1 = PWRDOWN/INTN is an Interrupt Output.
0 = PWRDOWN/INTN is a Power Down Input.
78 Register Block Copyright © 2011–2013, Texas Instruments Incorporated
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