Datasheet

DP83620

SNLS339C –JANUARY 2011–REVISED APRIL 2013

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7.4.6 Jabber Function

The jabber function monitors the DP83620's output and disables the transmitter if it attempts to transmit a

packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if

the transmitter is active for approximately 85 ms.

Once disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC

module's internal transmit enable is asserted. This signal has to be de-asserted for approximately 500 ms

(the “unjab” time) before the Jabber function re-enables the transmit outputs.

The Jabber function is only relevant in 10BASE-T mode.

7.4.7 Automatic Link Polarity Detection and Correction

The DP83620's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit.

When three consecutive inverted link pulses are received, bad polarity is reported. The bad polarity

condition is latched in the 10BTSCR register.

The DP83620's 10BASE-T transceiver module corrects for this error internally and will continue to decode

received data correctly. This eliminates the need to correct the wiring error immediately.

A polarity reversal can be caused by a wiring error at either end of the cable, usually at the Main

Distribution Frame (MDF) or patch panel in the wiring closet.

7.4.8 Transmit and Receive Filtering

External 10BASE-T filters are not required when using the DP83620, as the required signal conditioning is

integrated into the device.

Only isolation transformers and impedance matching resistors are required for the 10BASE-T transmit and

receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are

attenuated by at least 30 dB.

7.4.9 Transmitter

The encoder begins operation when the Transmit Enable input (TX_EN) goes high and converts NRZ data

to pre-emphasized Manchester data for the transceiver. For the duration of TX_EN, the serialized

Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD must be valid on the

rising edge of Transmit Clock (TX_CLK). Transmission ends when TX_EN de-asserts. The last transition

is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if

the last bit is a zero.

7.4.10 Receiver

The decoder consists of a differential receiver and a PLL to separate a Manchester encoded data stream

into internal clock signals and data. The differential input must be externally terminated with a differential

100 Ω termination network to accommodate UTP cable.

The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one

and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more

bit times after CRS goes low, to ensure the receive timings of the controller.

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