Datasheet

DP83620

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SNLS339C –JANUARY 2011–REVISED APRIL 2013

The PHY Control Frame may also be used to read a register location. The read value will be returned in a

PHY Status Frame if that function is enabled. Only a single read may be outstanding at any time, so only

one read should be included in a single PHY Control Frame.

The PHY Control Frame block performs the following functions:

• Parse incoming transmit packets to detect PHY Control Frames

• Truncate PHY Control Frames to prevent complete frame from reaching the transmit physical medium

• Buffer up to 15 bytes of the Frame to be intercepted by the PHY with no portion reaching physical

medium

• Detect commands in the PHY Control Frame and pass them to the register block

• Check CRC to detect error conditions

• Report CRC and invalid command errors to the system via register status and/or interrupt

PHY Control Frames can be enabled through the PCF_Enable bit in the PHY Control Frames

Configuration Register (PCFCR). PHY Control Frames can also be enabled by using the PCF_EN strap

option.

6.6 PHY STATUS FRAMES

The DP83620 implements a packet-based status mechanism that allows the PHY to generate status

messages indicating packet buffering errors and to return data read using the PHY Control Frame register

access mechanism.

Each PHY Status Frame may include multiple status messages. The PHY will provide buffering of any

incoming packet to allow the status packet to be passed to the MAC. Programmable inter-frame gap and

preamble length allow the PHY to recover lost bandwidth in the case of heavy receive traffic.

In a PHY Status Frame, status messages are not provided in a chronological order. Instead, they are

provided in the following order of priority:

1. PHY Control Frame Read Data

2. Packet Buffer Error

The packet format may be configured to look like a Layer 2 Ethernet frame or a UDP/IPv4 frame.

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