Datasheet

z
z
z
z
Register DataTA IdleRegister Address
(00h = BCMR)
PHY Address
(PHY AD = 0Ch)
Opcode
(Write)
StartIdle
MDC
MDIO
(STA)
0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 01
z
z
z
z
z
z
Register DataTA IdleRegister Address
(00h = BCMR)
PHY Address
(PHY AD = 0Ch)
Opcode
(Read)
StartIdle
MDC
MDIO
MDIO
(STA)
(PHY)
z
0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
DP83620
SNLS339C –JANUARY 2011–REVISED APRIL 2013 www.ti.com
The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle
line state.
Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field.
To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the
first bit of Turnaround. The addressed DP83620 drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data. Figure 6-1 shows the timing relationship between MDC
and the MDIO as driven/received by the Station (STA) and the DP83620 (PHY) for a typical register read
access.
For write transactions, the station management entity writes data to the addressed DP83620 thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting <10>. Figure 7-1 shows the timing relationship for a typical MII register write access.
Figure 6-1. Typical MDC/MDIO Read Operation
Figure 6-2. Typical MDC/MDIO Write Operation
6.4.3 Serial Management Preamble Suppression
The DP83620 supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode
Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management
controller) determines that all PHYs in the system support Preamble Suppression by returning a one in
this bit, then the station management entity need not generate preamble for each management
transaction.
The DP83620 requires a single initialization sequence of 32 bits of preamble following hardware/software
reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a
continuous MDC, or the management access made to determine whether Preamble Suppression is
supported.
While the DP83620 requires an initial preamble sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit
between management transactions is required as specified in the IEEE 802.3u specification.
6.5 PHY CONTROL FRAMES
The DP83620 supports a packet-based control mechanism for use in situations where the Serial
Management Interface is not available or does not provide enough throughput. Application software may
build a packet, called a PHY Control Frame (PCF), to be passed to the PHY through the MAC Transmit
Data interface. The PHY will intercept these packets and use them to assert writes to Management
Registers as if they occurred via the Management Interface. Multiple register writes may be incorporated
in a single frame.
48 MAC Interface Copyright © 2011–2013, Texas Instruments Incorporated
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