Datasheet

DP83620

SNLS339C –JANUARY 2011–REVISED APRIL 2013

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The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the

FIFO. Underrun and overrun conditions can be reported in the RMII and Bypass Register (RBR). Table 6-

1 indicates how to program the elasticity buffer FIFO (in 4-bit increments) based on expected maximum

packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter

clock) have the same accuracy.

Packet lengths can be scaled linearly based on accuracy (+/- 25 ppm would allow packets twice as large).

If the threshold setting must support both 10 Mb and 100 Mb operation, the setting should be made to

support both speeds.

Table 6-1. Supported Packet Sizes at +/-50 ppm Frequency Accuracy

Latency Tolerance Recommended Packet Size at +/- 50 ppm

Start Threshold RBR[1:0]

100 Mb 10 Mb 100 Mb 10 Mb

01 (default) 2 bits 8 bits 2,400 bytes 9,600 bytes

10 6 bits 4 bits 7,200 bytes 4,800 bytes

11 10 bits 8 bits 12,000 bytes 9,600 bytes

00 14 bits 12 bits 16,800 bytes 14,400 bytes

6.2.1 RMII Master Mode

In RMII Master Mode, the DP83620 uses a 25 MHz crystal on X1/X2 and internally generates the 50 MHz

RMII reference clock for use by the RMII logic. The 50 MHz clock is output on RX_CLK, TX_CLK, and

CLK_OUT for use as the reference clock for an attached MAC. RX_CLK operates at 25 MHz during reset.

6.2.2 RMII Slave Mode

In RMII Slave Mode, the DP83620 takes a 50 MHz reference clock input on X1 from an external oscillator

or another DP83620 in RMII Master Mode. The 50 MHz is internally divided down to 25 MHz for use as

the reference clock for non-RMII logic. RX_CLK, TX_CLK, and CLK_OUT should not be used as the RMII

reference clock in this mode but may be used for other system devices.

6.3 SINGLE CLOCK MII MODE

Single Clock MII (SCMII) Mode allows MII operation using a single 25 MHz reference clock. Normal MII

Mode requires three clocks, a reference clock for physical layer functions, a transmit MII clock, and a

receive MII clock. Similar to RMII mode, Single Clock MII mode requires only the reference clock. In

addition to reducing the number of pins required, this mode allows the attached MAC device to use only

the reference clock domain. AC Timing requirements for SCMII operation are similar to the RMII timing

requirements.

For 10 Mb operation, as in RMII mode, data is sampled and driven every 10 clocks since the reference

clock is at 10 times the data rate.

Separate control bits allow enabling the Transmit and Receive Single Clock modes separately, allowing

just transmit or receive to operate in this mode. Control of Single Clock MII mode is through the RBR

Single Clock MII mode incorporates the use of the RMII elasticity buffer, which is required to tolerate

potential frequency differences between the 25 MHz reference clock and the recovered receive clock.

Settings for the elasticity buffer for SCMII mode are detailed in Table 6-2.

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