Datasheet

DP83620

SNLS339C –JANUARY 2011–REVISED APRIL 2013

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Two different versions of the Frequency Offset may be monitored through bits [7:0] of register FREQ100

(15h). The first is the long-term Frequency Offset. The second is the current Frequency Control value,

which includes short-term phase adjustments and can provide information on the amount of jitter in the

system.

5.11.1.5 Cable Signal Quality Estimation

The cable signal quality estimator keeps a simple tracking of results of the DSP and can be used to

generate an approximate Signal-to-Noise Ratio for the 100 Mb receiver. This information is available to

software through the Link Diagnostics Registers - Page 2: Variance Control Register (VAR_CTRL),

address 1Ah and Variance Data Register (VAR_DATA), address 1Bh.

The variance computation times (VAR_TIMER) can be chosen from the set of {2, 4, 6, 8} ms. The 32-bit

variance sum can be read by two consecutive reads of the VAR_DATA register. This sum can be used to

compute an SNR estimate by software using the following equation:

SNR = 10log

((37748736 * VAR_TIMER) / Variance)

5.11.2 Link Quality Monitor

The Link Quality Monitor allows a method to generate an alarm when the DSP adaption strays from a

programmable window. This could occur due to changes in the cable which could indicate a potential

problem. Software can program thresholds for the following DSP parameters to be used to interrupt the

system:

— Digital Equalizer C1 Coefficient (DEQ C1)

— Digital Adaptive Gain Control (DAGC)

— Digital Base-Line Wander Control (DBLW)

— Recovered Clock Long-Term Frequency Offset (FREQ)

— Recovered Clock Frequency Control (FC)

— Signal-to-Noise Ratio (SNR) Variance

Software is expected to read initial adapted values and then program the thresholds based on an

expected valid range. This mechanism takes advantage of the fact that the DSP adaptation should remain

in a relatively small range once a valid link has been established.

5.11.2.1 Link Quality Monitor Control and Status

Control of the Link Quality Monitor is done through the Link Quality Monitor Register (LQMR), address

1Dh and the Link Quality Data Register (LQDR), address 1Bh of the Link Diagnostics Registers - Page 2.

The LQMR register includes a global enable to enable the Link Quality Monitor function. In addition, it

provides warning status from both high and low thresholds for each of the monitored parameters except

SNR Variance.. The LQMR2 register provides warning status for the high threshold of SNR Variance

(upper 16 bits); there is no low threshold. Note that individual low or high parameter threshold

comparisons can be disabled by setting to the minimum or maximum values.

To allow the Link Quality Monitor to interrupt the system, the Interrupt must be enabled through the

interrupt control registers, MICR (11h) and MISR (12h).

The Link Quality Monitor may also be used to automatically reset the DSP and restart adaption. Separate

enable bits in LQMR and LQMR2 allow for automatic reset based on each of the parameter values. If

enabled, a violation of one of the thresholds will result in a restart of the DSP adaption. In addition if the

PCSR:SD_OPTION register bit is set to 0, the violation will also result in a drop in Link Status.

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