Datasheet

2.2 k:
PHYAD1 = 1PHYAD2 = 0PHYAD3 = 0PHYAD4 = 0
VCC
RXD
_
0
RXD_1 RXD
_
2
RXD
_
3
COL
PHYAD0 = 1
DP83620
www.ti.com SNLS339C –JANUARY 2011–REVISED APRIL 2013
Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pull-
down resistors, the default setting for the PHY address is 00001 (01h).
Refer to Figure 5-1 for an example of a PHYAD connection to external components. In this example, the
PHYAD strapping results in address 00011 (03h).
Figure 5-1. PHYAD Strapping Example
5.5.1 MII Isolate Mode
It is recommended that the user have a basic understanding of Clause 22 of the 802.3u standard.
The DP83620 can be put into MII Isolate Mode by writing a 1 to bit 10 of the BMCR register. Strapping the
PHY Address to 0 will force the device into Isolate Mode when powered up. It should be noted that
selecting Physical Address 0 via an MDIO write to PHYCR will not put the device in the MII isolate mode.
When in the MII Isolate Mode, the DP83620 does not respond to packet data present at TXD[3:0] and
TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0],
COL, and CRS/CRS_DV outputs. When in Isolate Mode, the DP83620 will continue to respond to all serial
management transactions over the MII.
While in Isolate Mode, the PMD output pair will not transmit packet data but will continue to source
100BASE-TX scrambled idles or 10BASE-T normal link pulses.
The DP83620 can Auto-Negotiate or parallel detect to a specific technology depending on the receive
signal at the PMD input pair. A valid link can be established for the receiver even when the DP83620 is in
Isolate Mode.
5.5.2 Broadcast Mode
The DP83620 is also capable of accepting broadcast messages (register writes to PHY address 0x1F).
Setting the BC_WRITE to 1, bit 11 of the PHY Control Register 2 (PHYCR2) at address 0x1C, will
configure the device to accept broadcast messages independent of the local PHY Address value.
5.6 LED INTERFACE
The DP83620 supports three configurable Light Emitting Diode (LED) pins: LED_LINK,
LED_SPEED/FX_SD, and LED_ACT.
Several functions can be multiplexed onto the three LEDs using three different modes of operation. The
LED operation mode can be selected by writing to the LED_CFG[1:0] register bits in the PHY Control
Register (PHYCR) at address 19h, bits [6:5]. LED_CFG[1] is only controllable through register access and
cannot be set by a strap pin.
See Table 5-3 for LED Mode selection.
Copyright © 2011–2013, Texas Instruments Incorporated Configuration 35
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