Datasheet

DP83620
SNLS339C JANUARY 2011REVISED APRIL 2013
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3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE
Signal Name Pin Name Type Pin # Description
TD- TD- I/O 16 Differential common driver transmit output (PMD Output Pair). These
TD+ TD+ 17 differential outputs are automatically configured to either 10BASE-T or
100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive Input
pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Transmit pair.
These pins require 3.3V bias for operation.
RD- RD- I/O 13 Differential receive input (PMD Input Pair). These differential inputs are
RD+ RD+ 14 automatically configured to accept either 100BASE-TX or 10BASE-T
signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit
Output pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.
These pins require 3.3V bias for operation.
FX_SD LED_SPEED/FX_S S, I/O, PU 27 FIBER MODE SIGNAL DETECT: This pin provides the Signal Detect input
D for 100BASE-FX mode.
3.11 RESERVED PINS
Signal Name Pin Name Type Pin # Description
RESERVED RESERVED I/O 23 RESERVED: These pins are reserved and should not be connected to any
25 external logic or net for most implementations. For JTAG implementations,
36 these pins should be connected to GND (0) or V
CC
(1) through 2.2 k
37 resistors. These pins should NEVER be connected directly to GND or
V
CC
.
3.12 POWER SUPPLY PINS
Signal Name Pin Name Type Pin # Description
ANAVSS ANAVSS Ground 18 Analog Ground
ANA33VDD ANA33VDD Supply 19 Analog VDD Supply
CD_VSS CD_VSS Ground 15 Analog Ground
IO_CORE_VSS IO_CORE_VSS Ground 35 Digital Ground
IO_VDD IO_VDD Supply 32 I/O VDD Supply
48
IO_VSS IO_VSS Ground 47 Digital Ground
VREF VREF 20 Bias Resistor Connection. A 4.87 k 1% resistor should be connected from
VREF to GND.
DAP DAP No Connect or Connect to GND
(1)
(1) Die Attach Pad (DAP) provides thermal dissipation. Connection to GND plane recommended.
12 Pin Descriptions Copyright © 2011–2013, Texas Instruments Incorporated
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