Datasheet
SN75DP130
SLLSE57D –APRIL 2011–REVISED JULY 2013
www.ti.com
Table 8. SN75DP130 Local I
2
C Control and Status Registers
ACCESS
(
ADDRESS BIT(S) DESCRIPTION
1)
AUTO_POWERDOWN_DISABLE
1 0 – The SN75DP130 automatically enters Standby mode based on HPD_SNK (default) RW
1 – The SN75DP130 will not automatically enter Standby mode
01h
FORCE_SHUTDOWN_MODE
0 0 – SN75DP130 is forced to Shutdown mode RW
1 – Shutdown mode is determined by EN input, normal operation (default)
02h 7:0 TI_TEST. This field defaults to zero value, and should not be modified. RW
SQUELCH_SENSITIVITY. Main Link squelch sensitivity is selected by this field, and
determines the transitions to and from the Output Disable mode.
00 – Main Link IN0p/n squelch detection threshold set to 40mVpp
5:4 RW
01 – Main Link IN0p/n squelch detection threshold set to 80mVpp (default)
10 – Main Link IN0p/n squelch detection threshold set to 160mVpp
03h
11 – Main Link IN0p/n squelch detection threshold set to 250mVpp
SQUELCH_ENABLE
3 0 – Main Link IN0p/n squelch detection enabled (default) RW
1 – Main Link IN0p/n squelch detection disabled
3 TI_TEST. This field defaults to zero value, and should not be modified. RW
LINK_TRAINING_ENABLE
0 – Link Training is disabled. V
OD
and Pre-emphasis are configured through the I
2
C register
2 RW
interface; the EQ is fixed when this bit is zero.
1 – Link Training is enabled (default)
04h
AUX_DDC_MUX_CFG. See Table 3 for details on the programming of this field.
00 – AUX_SNK is switched to AUX_SRC for DDC source side based on CAD_SNK (default)
01 – AUX_SNK is switched to AUX_SRC based on the CAD_SNK input, and used to short
1:0 circuit AC coupling capacitors in the TMDS operating mode. RW
10 – AUX_SNK is switched to AUX_SRC side based on the HPD_SNK inptu, while the DDC
source interface remains disabled.
11 – Undefined operation
EQ_I2C_ENABLE
7 0 – EQ settings controlled by device inputs only (default) RW
1 – EQ settings controlled by I
2
C register settings
AEQ_L0_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE
is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results
in Level 0 pre-emphasis.
000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2)
6:4 RW
001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2)
010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2)
011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2)
05h
2:0 AEQ_L1_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE RW
is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results
in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following non-
AEQ modes:
MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled
MM ● I2C_EQ_ENABLE is set and the TMDS sink is selected.
000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2)
001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2)
010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2)
011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2)
(1) RO = Read Only; RW = Read/Write; WO = Write Only (reads return undetermined values)
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