Datasheet

SN75DP130
SLLSE57D –APRIL 2011–REVISED JULY 2013 www.ti.com
A. DisplayPort output jitter measured at the surface mount pins
connected to the main link output channels on the SN75DP130
characterization test board; input jitter generated from test board with
variable input trace lengths using 4 mil traces of lengths 2 inches to
22 inches generating the typical input jitter as represented in Table 1.
Figure 17. TMDS Sink jitter Performance with Optimal EQ Figure 18. Main Link Input with 10 inch Trace; DisplayPort
Settings Sink
Figure 19. SN75DP130 Output; 10 inch Input Trace; 13dB Figure 20. Main Link Input with 10 inch Trace; TMDS Sink
EQ Setting; DP Sink
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