Datasheet
SN75DP130
www.ti.com
SLLSE57D –APRIL 2011–REVISED JULY 2013
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 V
V
DDD
Digital core and Main Link supply voltage 0.97 1.05 1.2 V
T
A
Operating free-air temperature 0 85 °C
T
CASE
Case temperature 103.1 °C
V
IH(HPD)
High-level input voltage HPD_SNK 1.9 5.5 V
1.9 3.6
High-level input voltage for device
V
IH
V
control signals
RSTN pin (typical hysteresis of 80mV) 0.75
0 0.8
Low-level input voltage for device
V
IL
V
control signals
RSTN pin (typical hysteresis of 80mV) 0.30
MAIN LINK TERMINALS
V
ID
Peak-to-peak input differential voltage; RBR, HBR, HBR2 0.30 1.40 Vpp
d
R
Data rate 5.4 Gbps
C
AC
AC coupling capacitance (each input and each output line) 75 200 nF
R
tdiff
Differential output termination resistance 80 100 120 Ω
V
Oterm
Output termination voltage (AC coupled) 0 2 V
When used as re-driver in DP source 20
Intra-pair skew at the input at
t
SK(in HBR2)
ps
5.4Gbps
When used as receiver equalizer in DP sink 100
t
SK(in HBR)
Intra-pair skew at the input at 2.7Gbps 100 ps
t
SK(in RBR)
Intra-pair skew at the input at 1.62Gbps 300 ps
AUX CHANNEL DATA TERMINALS
AUX_SRCp and AUX_SNKp in DP mode -0.5 0.3 0.4
V
I-DC
DC input voltage AUX_SRCn and AUX_SNKn in DP mode 2.0 3.0 3.6 V
AUX_SRCp/n and AUX_SNKp/n in TMDS mode -0.5 3.6
V
ID
Differential input voltage amplitude (DP mode only) 300 1400 mV
PP
d
R(AUX)
Data rate (before Manchester encoding) 0.8 1 1.2 Mbps
d
R(FAUX)
Data rate Fast AUX (300ppm frequency tolerance) 720 Mbps
t
jccin_adj
Cycle-to-cycle AUX input jitter adjacent cycle (DP mode only) 0.05 UI
t
jccin
Cycle-to-cycle AUX input jitter within one cycle (DP mode only) 0.1 UI
C
AC
AUX AC coupling capacitance (DP mode only) 75 200 nF
AUX source common mode voltage (only applies to DP mode)
V
srcCMM
0 2000 mV
CAD = V
IL
; measured on AUX source and sink before AC coupling caps
DDC AND I
2
C TERMINALS
V
I
Input voltage -0.5 3.6 V
d
R
Data rate 100 kbps
V
IH
High-level input voltage 0.7V
CC
V
V
IL
Low-level input voltage 0.3V
CC
V
f
SCL
SCL clock frequency standard I
2
C mode 100 kHz
t
w(L)
SCL clock low period standard I
2
C mode 4.7 µs
t
w(H)
SCL clock high period standard I
2
C mode 4.0 µs
C
bus
Total capacitive load for each bus line 400 pF
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