Datasheet

T > 100 µs
Time
RSTN
Vcc for SS and DS
Vddd for DS
T > 10 µs
Vcc Vcc
Vddd
(DP130DS only)
Vddd
(DP130DS only)
T > 400 ms
Device
Available
SN75DP130
SLLSE57D –APRIL 2011–REVISED JULY 2013 www.ti.com
PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NAME NO.
SN75DP130SS: Digital voltage regulator decoupling; install 1µF to GND.
VDDD_DREG 2 SN75DP130DS: Treat same as VDDD; this pin will be most noisy of all VDDD
terminals and needs a de-coupling capacitor nearby.
18, 24, 31, and Ground. Reference GND connections include the device package exposed thermal
GND
Exposed Thermal Pad pad.
SN75DP130SS
7, 15, 21, 37, 40, 43, 46
NC No Connect. These terminals may be left unconnected, or connect to GND.
SN75DP130DS
7, 40, 46
DP130 POWER SEQUENCING
The following power-up and power-down sequences describe how the RSTN signal is applied to the
SN75DP130.
Power-Up Sequence:
1. Apply V
cc
with less than a 10-ms ramp time for the DP130SS and for the DP130DS, apply V
ddd
then V
cc
(both
having less than 10-ms ramp time) devices. V
ddd
must be asserted first and stable for greater than 10 µs
before V
cc
is applied.
2. RSTN must remain asserted until V
cc
/V
ddd
voltage has reached minimum recommended operation for more
than 100 µs.
3. De-assert RSTN (Note: This RSTN is a 1.05-V interface and is internally connected to V
ddd_dreg
through a
150-kΩ resistor).
4. Device will be available for operation approximately 400 ms after a valid reset.
Power-Down Sequence:
1. Assert RSTN to the device.
2. Remove V
cc
and V
ddd
.
Figure 5. Power-Up and Power-Down Sequence
6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: SN75DP130