Datasheet

DLP4500

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DLPS028A –APRIL 2013–REVISED MAY 2013

Figure 2. Typical Application

Electrically, the DLP4500 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of

912 memory cell columns by 1140 memory cell rows. The CMOS memory array is addressed on column-by-

column basis, over a 24-bit double data rate (DDR) bus. Addressing is handled via a serial control bus. The

specific CMOS memory access protocol is handled by the DLPC350 digital controller.

Optically, the DLP4500 consists of 1,039,680 highly reflective, digitally switchable, micrometer-sized mirrors

(micromirrors) organized in a two-dimensional array. The micromirror array consists of 912 micromirror columns

by 1140 micromirror rows in diamond pixel configuration (Figure 3). Due to the diamond pixel configuration, the

columns of each odd row are offset by half a pixel from the columns of the even row.

Each aluminum micromirror is approximately 7.6 microns in size (see Micromirror Pitch in Figure 3), and is

switchable between two discrete angular positions: –12° and +12°. The angular positions α and β are measured

relative to a 0° flat reference when the mirrors are parked in their inactive state, parallel to the array plane (see

Figure 4). The parked position is not a latched position. Individual micromirror angular positions are relatively flat,

but will vary. The tilt direction is perpendicular to the hinge-axis. The on-state landed position is directed toward

the left side of the package (see Figure 3).

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a

specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell

contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual

micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the

CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking

pulse results in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell

followed by a mirror clocking pulse results in the corresponding micromirror switching to a –12° position.

Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the

CMOS memory. Second, application of a mirror reset to all or a portion of the micromirror array (depending upon

the configuration of the system). Mirror reset pulses are generated internally by the DLP4500 DMD, with

application of the pulses being coordinated by the DLPC350 controller. See Switching Characteristics for timing

specifications.

Around the perimeter of the 912 × 1140 array of micromirrors is a uniform band of border micromirrors. The

border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has

been applied to the device. There are 10 border micromirrors on each side of the 912 by 1140 active array.

Product Folder Links: DLP4500