Datasheet

DLP4500
www.ti.com DLPS028A –APRIL 2013–REVISED MAY 2013
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Setup time: DATA before rising or falling edge of DCLK
(1)
0.7
t
s1
Setup time: TRC before rising or falling edge of DCLK
(1)
0.7 ns
Setup time: SCTRL before rising or falling edge of DCLK
(1)
0.7
t
s2
Setup time: LOADB low before rising edge of DCLK
(1)
0.7 ns
t
s3
Setup time: SAC_BUS low before rising edge of SAC_CLK
(1)
1 ns
t
s4
Setup time: DRC_BUS high before rising edge of SAC_CLK
(1)
1 ns
t
s5
Setup time: DRC_STROBE high before rising edge of SAC_CLK
(1)
1 ns
Hold time: DATA after rising or falling edge of DCLK
(1)
0.7
t
h1
Hold time: TRC after rising or falling edge of DCLK
(1)
0.7 ns
Hold time: SCTRL after rising or falling edge of DCLK
(1)
0.7
t
h2
Hold time: LOADB low after falling edge of DCLK
(1)
0.7 ns
t
h3
Hold time: SAC_BUS low after rising edge of SAC_CLK
(1)
1 ns
t
h4
Hold time: DRC_BUS after rising edge of SAC_CLK
(1)
1 ns
t
h5
Hold time: DRC_STROBE after rising edge of SAC_CLK
(1)
1 ns
t
c1
Clock cycle: DCLK 8.33 10 12.5 ns
13.3
t
c3
Clock cycle: SAC_CLK 12.5 14.3 ns
3
t
w1
Pulse width high or low: DCLK 3.33 ns
t
w2
Pulse width low: LOADB 4.73 ns
t
w3
Pulse width high or low: SAC_CLK 5 ns
t
w5
Pulse width high: DRC_STROBE 7 ns
Rise time (20% - 80%): DCLK / SAC_CLK VREF = 1.8V 1.08
t
r
ns
Rise time (20% - 80%): DATA / TRC / SCTRL / LOADB VREF = 1.8V 1.08
Fall time (20% - 80%): DCLK / SAC_CLK VREF = 1.8V 1.08
t
f
ns
Fall time (20% - 80%): DATA / TRC / SCTRL / LOADB 1.08
(1) For fast input slew rate > 1 V/ns. For slow slew rates > 0.5ns and < 1ns, the setup and hold times will be longer. For every 0.1V
decrease in slew rate from 1 V/ns, add 150 picoseconds on setup and hold. The numbers assume all the slew rates for all the inputs
and the clock are the same.
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