Datasheet
From Output
Under Test
R
L
Tester Channel
C = 50 pF
C = 5 pF for Disable Time
L
L
DLP4500
DLPS028A –APRIL 2013–REVISED MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)
PARAMETER CONDITIONS MIN NOM MAX UNIT
V
OH
High-level output voltage V
CC
= 2.5 V, I
OH
= –21 mA 1.7 V
V
OL
Low-level output voltage V
CC
= 2.5 V, I
OH
= 15 mA 0.4 V
I
OH
High-level output current V
OH
= 1.4 V -9 mA
I
OL
Low-level output current V
OL
= 0.4 V 18 mA
I
IL
Low-level input current
(1)
V
REF
= 2.00 V V
I
= 0 V –50 nA
I
IH
High-level input current
(1)
VREF = 2.00 V V
I
= VREF 50 nA
I
REF
Current into VREF terminal VREF = 2.00 V f
DCLK
= 120 MHz 2.15 2.75 mA
I
CC
Current into VCC terminal VCC = 2.75 V f
DCLK
= 120 MHz 125 160 mA
3 Global Resets
Current into VOFFSET
I
OFFSET
VOFFSET = 8.75 V within Time Period = 3 3.3 mA
terminal
(2)
200μs
3 Global Resets
Current into VBIAS
I
BIAS
VBIAS = 16.5 V within Time Period = 2.55 3.55 mA
terminal
(2)(3)
200μs
I
RESET
Current into VRESET terminal VRESET = –10.5 V 2.45 3.10 mA
P
REF
Power into VREF terminal
(4)
VREF = 2.00 V f
DCLK
= 120 MHz 3.87 5.50 mW
P
CC
Power into VCC terminal
(4)
VCC = 2.75 V f
DCLK
= 120 MHz 312.5 440.0 mW
P
OFFSET
3 Global Resets
Power into VOFFSET
VOFFSET = 8.75 V within Time Period = 25.5 28.9 mW
terminal
(4)
200μs
P
BIAS
3 Global Resets
Power into VBIAS terminal
(4)
VBIAS = 16.5 V within Time Period = 40.8 58.6 mW
200μs
Power into VRESET
P
RESET
VRESET = –10.5 V 24.5 32.6 mW
terminal
(4)
C
I
Input capacitance f = 1 MHz 10 pF
C
O
Output capacitance f = 1 MHz 10 pF
(1) Applies to LVCMOS pins only. LVCMOS pins do not have pull-up or pull-down configurations.
(2) Exceeding the maximum allowable absolute voltage difference between VBIAS and VOFFSET may result in excesses current draw. See
the Absolute Maximum Ratings for further details.
(3) When DRC_OE = High, the internal reset drivers are tri-stated and I
BIAS
standby current is 6.5mA.
(4) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See the Thermal
Characteristics for further details.
Measurement Conditions
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 12 shows an equivalent test load circuit for the
output under test. The load capacitance value stated is only for characterization and measurement of ac timing
signals. This load capacitance value does not indicate the maximum load the device is capable of driving.
Figure 12. Test Load Circuit for AC Timing Measurements
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