Datasheet

DLP4500
www.ti.com
DLPS028A APRIL 2013REVISED MAY 2013
Table 4. Connector Pins for FQD (continued)
TERMINAL CONNECTOR INTERNAL CLOCKED DATA
I/O/P TYPE DESCRIPTION
NAME PINS TERMINATION BY RATE
B22, C2, D21, Power Supply for LVCMOS Logic
E2, E20, E22,
F21, G3, G19,
VCC Power Analog None
G20, G22,
H19, H21, J20,
J22, K21
A21, B2, B4,
B20, C21, D2,
D3, D20, D22,
E3, E21, F2, Ground - Common return for all
VSS Power Analog None
F4, F20, F22, power inputs
G21, H3, H20,
H22, J2, J21,
K20
A5, A18, B5,
B18, C5, C18,
D5, D18, E5,
For proper device operation, leave
No connect E18, F5, F18,
these terminals unconnected.
G5, G18, H5,
H18, J5, J18,
K22
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: DLP4500