Datasheet
DLP4500
DLPS028A –APRIL 2013–REVISED MAY 2013
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Table 4. Connector Pins for FQD
TERMINAL CONNECTOR INTERNAL CLOCKED DATA
I/O/P TYPE DESCRIPTION
NAME PINS TERMINATION BY RATE
Data Inputs
DATA(0) A1 Input LVCMOS None DCLK DDR
DATA(1) A2 Input LVCMOS None DCLK DDR
DATA(2) A3 Input LVCMOS None DCLK DDR
DATA(3) A4 Input LVCMOS None DCLK DDR
DATA(4) B1 Input LVCMOS None DCLK DDR
DATA(5) B3 Input LVCMOS None DCLK DDR
DATA(6) C1 Input LVCMOS None DCLK DDR
DATA(7) C3 Input LVCMOS None DCLK DDR
DATA(8) C4 Input LVCMOS None DCLK DDR
DATA(9) D1 Input LVCMOS None DCLK DDR
DATA(10) D4 Input LVCMOS None DCLK DDR
DATA(11) E1 Input LVCMOS None DCLK DDR
Input data bus
DATA(12) E4 Input LVCMOS None DCLK DDR
DATA(13) F1 Input LVCMOS None DCLK DDR
DATA(14) F3 Input LVCMOS None DCLK DDR
DATA(15) G1 Input LVCMOS None DCLK DDR
DATA(16) G2 Input LVCMOS None DCLK DDR
DATA(17) G4 Input LVCMOS None DCLK DDR
DATA(18) H1 Input LVCMOS None DCLK DDR
DATA(19) H2 Input LVCMOS None DCLK DDR
DATA(20) H4 Input LVCMOS None DCLK DDR
DATA(21) J1 Input LVCMOS None DCLK DDR
DATA(22) J3 Input LVCMOS None DCLK DDR
DATA(23) J4 Input LVCMOS None DCLK DDR
DCLK K1 Input LVCMOS None – – Input data bus clock
Data Control Inputs
LOADB K2 Input LVCMOS None DCLK DDR Parallel data load enable
TRC K4 Input LVCMOS None DCLK DDR Input data toggle rate control
SCTRL K3 Input LVCMOS None DCLK DDR Serial control bus
Stepped address control serial bus
SAC_BUS C20 Input LVCMOS None SAC_CLK –
data
Stepped address control serial bus
SAC_CLK C22 Input LVCMOS None – –
clock
Mirror Reset Control Inputs
DRC_BUS B21 Input LVCMOS None SAC_CLK DMD reset-control serial bus
Active-low output enable signal for
DRC_OE A20 Input LVCMOS None – –
internal DMD Reset driver circuitry
Strobe signal for DMD Reset
DRC_STROBE A22 Input LVCMOS None SAC_CLK
Control inputs
Power
VBIAS C19, D19 Power Analog None – – Mirror Reset Bias Voltage
VOFFSET A19, K19 Power Analog None – – Mirror Reset Offset Voltage
VRESET E19, F19 Power Analog None – – Mirror Reset Voltage
Power Supply for Low Voltage
VREF B19, J19 Power Analog None – – CMOS Double-Data-Rate (DDR)
Interface
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