Datasheet

DLP5500
www.ti.com DLPS013E –APRIL 2010–REVISED SEPTEMBER 2013
Internal
TERMINAL PIN INTERNAL CLOCKED Trace DATA
I/O/P TYPE DESCRIPTION
NAME See Figure 6 TERMINATION BY Length RATE
(mils)
(1)
Data Inputs
D_AN1 G20 Input LVCMOS Differential Terminated DCLK_A 715 LVDS
D_AP1 H20 Input LVCMOS Differential Terminated DCLK_A 744 LVDS
D_AN3 H19 Input LVCMOS Differential Terminated DCLK_A 688 LVDS
D_AP3 G19 Input LVCMOS Differential Terminated DCLK_A 703 LVDS
D_AN5 F18 Input LVCMOS Differential Terminated DCLK_A 686 LVDS
D_AP5 G18 Input LVCMOS Differential Terminated DCLK_A 714 LVDS
D_AN7 E18 Input LVCMOS Differential Terminated DCLK_A 689 LVDS
D_AP7 D18 Input LVCMOS Differential Terminated DCLK_A 705 LVDS
Input data bus A
D_AN9 C20 Input LVCMOS Differential Terminated DCLK_A 687 LVDS
D_AP9 D20 Input LVCMOS Differential Terminated DCLK_A 715 LVDS
D_AN11 B18 Input LVCMOS Differential Terminated DCLK_A 715 LVDS
D_AP11 A18 Input LVCMOS Differential Terminated DCLK_A 732 LVDS
D_AN13 A20 Input LVCMOS Differential Terminated DCLK_A 686 LVDS
D_AP13 B20 Input LVCMOS Differential Terminated DCLK_A 715 LVDS
D_AN15 B19 Input LVCMOS Differential Terminated DCLK_A 700 LVDS
D_AP15 A19 Input LVCMOS Differential Terminated DCLK_A 719 LVDS
D_BN1 K20 Input LVCMOS Differential Terminated DCLK_B 716 LVDS
D_BP1 J20 Input LVCMOS Differential Terminated DCLK_B 745 LVDS
D_BN3 J19 Input LVCMOS Differential Terminated DCLK_B 686 LVDS
D_BP3 K19 Input LVCMOS Differential Terminated DCLK_B 703 LVDS
D_BN5 L18 Input LVCMOS Differential Terminated DCLK_B 686 LVDS
D_BP5 K18 Input LVCMOS Differential Terminated DCLK_B 714 LVDS
D_BN7 M18 Input LVCMOS Differential Terminated DCLK_B 693 LVDS
D_BP7 N18 Input LVCMOS Differential Terminated DCLK_B 709 LVDS
Input data bus B
D_BN9 P20 Input LVCMOS Differential Terminated DCLK_B 687 LVDS
D_BP9 N20 Input LVCMOS Differential Terminated DCLK_B 715 LVDS
D_BN11 R18 Input LVCMOS Differential Terminated DCLK_B 702 LVDS
D_BP11 T18 Input LVCMOS Differential Terminated DCLK_B 719 LVDS
D_BN13 T20 Input LVCMOS Differential Terminated DCLK_B 686 LVDS
D_BP13 R20 Input LVCMOS Differential Terminated DCLK_B 715 LVDS
D_BN15 R19 Input LVCMOS Differential Terminated DCLK_B 680 LVDS
D_BP15 T19 Input LVCMOS Differential Terminated DCLK_B 700 LVDS
DCLK_AN D19 Input LVCMOS Differential Terminated – 700 –
Input data bus A
Clock
DCLK_AP E19 Input LVCMOS Differential Terminated – 728 –
DCLK_BN N19 Input LVCMOS Differential Terminated – 700 –
Input data bus B
Clock
DCLK_BP M19 Input LVCMOS Differential Terminated – 728 –
Data Control Inputs
SCTRL_AN F20 Input LVCMOS Differential Terminated DCLK_A 716 LVDS
SCTRL_AP E20 Input LVCMOS Differential Terminated DCLK_A 731 LVDS
SCTRL_BN L20 Input LVCMOS Differential Terminated DCLK_B 707 LVDS
SCTRL_BP M20 Input LVCMOS Differential Terminated DCLK_B 722 LVDS
Serial Communication and Configuration
SCP_CLK A8 Input LVCMOS pull-down – – –
SCP_DO A9 Output LVCMOS – SCP_CLK – –
SCP_DI A5 Input LVCMOS pull-down SCP_CLK – –
SCP_EN B7 Input LVCMOS pull-down SCP_CLK – –
PWRDN B9 Input LVCMOS pull-down – – –
MODE_A A4 Input LVCMOS pull-down – – –
(1) Internal Trace Length (mils) refers to the Package electrical trace length. See the DLP 0.55 XGA Chip-Set Data Sheet (TI literature
number DLPS012) for details regarding signal integrity considerations for end-equipment designs.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DLP5500