Datasheet

DLPC200
Port 1 Data Interface
DMD_DAT_A( 1, 3, 5, 7, 9, 11, 13, 15 )
P/N
SCTRL_A
P/N
SCP_DMD_RST_DO
SCP_DMD_RST_CLK
DMD_DAT_B( 1, 3, 5, 7, 9, 11, 13, 15 )
P/N
SCTRL_B
P/N
DMD_PWRDN
DMD_CLK_A
P/N
DMD_CLK_B
P/N
User Static Memory Interface
Port 2 Data Interface
User Nonvolatile Memory Interface
USB Interface
CFG_MSEL( 3:0 )
CFG_ASDI
CFG_ASDO
CFG_CSO
CFG_CLK
V
3P3V
V
SS
Serial Port Interface
SCP_DMD_RST_DI
SCP_DMD_EN
SCP_DMD_RST_CLK
SCP_DMD_RST_DO
SCP_DMD_RST_DI
MBRST( 15:0 )
RST_A( 3:0 )
RST_MODE( 1:0 )
RST_SEL( 1:0 )
RST_OE
RST_STB
RST_RST
RST_IRQ
DLP5500
Data & Control Receiver
DLPA200
V
CC
V
CC2
V
SS
V
CCI
Illumination Interface
V
OFFSET
V
BIAS
V
RST
V
CC
V
12V
SCP_DMD_EN
Sync Out Interface
V
3P3V
V
VCCA
V
CCD_PLL
V
1P2V
V
1P8V
V
2P5V
V
CCA_PLL
V
SS
DMD Interface
CMOS
MEMORY
ARRAY
MICROMIRROR
ARRAY
DLPA200 Interface
Configuration Interface
DLPR200F
DLPR200F PROM
DLP5500
DLPS013E APRIL 2010REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
Figure 1. Block Diagram of 0.55 XGA Chipset
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Product Folder Links: DLP5500