Datasheet

DLP5500
DLPS013E –APRIL 2010–REVISED SEPTEMBER 2013 www.ti.com
Internal
TERMINAL PIN INTERNAL CLOCKED Trace DATA
I/O/P TYPE DESCRIPTION
NAME See Figure 6 TERMINATION BY Length RATE
(mils)
(1)
Micromirror Bias Reset
MBRST0 C3 Input Analog – – – –
MBRST1 D2 Input Analog – – – –
MBRST2 D3 Input Analog – – – –
MBRST3 E2 Input Analog – – – –
MBRST4 G3 Input Analog – – – –
MBRST5 E1 Input Analog – – – –
Micromirror Bias
Reset "MBRST"
MBRST6 G2 Input Analog – – – –
signals "clock"
MBRST7 G1 Input Analog – – – –
micromirrors into
state of LVCMOS
MBRST8 N3 Input Analog – – – –
memory cell
MBRST9 M2 Input Analog – – – –
associated with
each mirror.
MBRST10 M3 Input Analog – – – –
MBRST11 L2 Input Analog – – – –
MBRST12 J3 Input Analog – – – –
MBRST13 L1 Input Analog – – – –
MBRST14 J2 Input Analog – – – –
MBRST15 J1 Input Analog – – – –
Power
B11,B12,B13,B1
Power for LVCMOS
V
CC
6,R12,R13,R16, Power Analog – – – –
Logic
R17
A12,A14,A16,T1 Power supply for
V
CCI
Power Analog – – – –
2,T14,T16 LVDS Interface
Power for High
V
CC2
C1,D1,M1,N1 Power Analog – – – – Voltage CMOS
Logic
A6,A11,A13,A15, –
A17,B4,B5,B8,B1
4,B15,B17,C2,C1
8,C19,F1,F2,F19,
Common return for
V
SS
H1,H2,H3,H18,J1 Power Analog – – –
all power inputs
8,K1,K2,L19,N2,
P18,P19,R4,R9,
R14,R15,T7,T13,
T15,T17
Reserved Signals (Not for use in system)
RESERVED_R7 R7 input LVCMOS pull-down – – –
RESERVED_R8 R8 input LVCMOS pull-down – – –
Pins should be
connected to V
SS
RESERVED_T8 T8 input LVCMOS pull-down – – –
RESERVED_B6 B6 input LVCMOS pull-down – – –
A3, A7, A10, B2, DO NOT CONNECT
B3, B10, E3, F3,
K3, L3, P1, P2,
P3, R1, R2, R3,
NO_CONNECT – – – – – –
R5, R6, R10,
R11, T1, T2, T3,
T4, T5, T6, T9,
T10, T11
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