Datasheet

■ Feedback modes: The logic that implements the various feedback modes supported by AES.
■ GHASH core: The polynomial multiplication algorithm used for AES-GCM
■ AES key scheduler: Generates AES encryption and decryption (round) keys
■ AES encryption core: The AES encryption algorithm
■ AES decryption core: The AES decryption algorithm
■ Substitution-boxes (S-Boxes): Contain AES S-Box GF(2
8
) implementations
AES encryption requires a specific number of rounds, depending on the key length. The supported
key lengths are 128-, 192-, and 256-bit, which require 10, 12, and 14 rounds, respectively, or 32,
38, and 44 clock cycles, respectively, because {number of clock cycles} = 2 + 3 x {number of rounds}.
The larger key lengths provide greater encryption strength at the expense of additional rounds and
therefore reduced throughput. The overall throughput of the AES executing polynomial multiplication
is adjusted based on the overall cryptographic performance. The AES module contains one Electronic
Codebook (ECB) core and a dedicated 32-cycle polynomial multiplication module for performing
GHASH operations. Polynomial multiplication operates in parallel with the AES core, if data is
available for both modules.
Depending on the key size (128/192/256 bits), this core requires 32, 38, or 44 clock cycles to process
one 128-bit data block. While one data block processes, the next block can be preloaded immediately.
When a block is preloaded, the previous block must finish before additional data can be loaded.
Therefore, once the pipeline is full, sequential data blocks can be passed every 32, 38, or 44 clock
cycles.
13.2.1.1 Interfaces
The interface signals to the AES module can be grouped into the following four categories:
■ Clock and reset signals
■ Register interface
■ µDMA/INT interface, used to request new context and packet data or to indicate available result
data (encrypted/decrypted data or authentication result)
13.2.1.2 Register Interface
The register interface block performs all address decoding and control. However, not all registers
are located in this block. The context and data input registers are in the AES wide-bus engine. The
data output registers are available in this block.
13.2.1.3 AES Wide-Bus Engine
The AES wide-bus engine performs the cryptographic operations. The composition of the AES core
is:
■ The main data path operates on the input block, performing the required substitution, shift, and
mix operations.
■ The key scheduler generates the round keys. A new subkey is generated and XORed with the
data each round.
December 13, 2013988
Texas Instruments-Advance Information
Advance Encryption Standard Accelerator (AES)