Datasheet

Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020
Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030
This register selects the size of transactions when performing non-blocking reads with the
EPIRPSTDn registers. This size affects how the external address is incremented.
The SIZE field must match the external data width as configured in the EPIHBnCFG or EPIGPCFG
register.
SDRAM mode uses a 16-bit data interface. If SIZE is 0x1, data is returned on the least significant
bits (D[7:0]), and the remaining bits D[31:8] are all zeros, therefore the data on bits D[15:8] is lost.
If SIZE is 0x2, data is returned on the least significant bits (D[15:0]), and the remaining bits D[31:16]
are all zeros.
Note that changing this register while a read is active has an unpredictable effect.
EPI Read Size n (EPIRSIZEn)
Base 0x400D.0000
Offset 0x020
Type RW, reset 0x0000.0003
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SIZEreserved
RWRWROROROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:2
Current Size
DescriptionValue
reserved0x0
Byte (8 bits)0x1
Half-word (16 bits)0x2
Word (32 bits)0x3
0x3RWSIZE1:0
December 13, 2013926
Texas Instruments-Advance Information
External Peripheral Interface (EPI)