Datasheet

18.4.1 Module Initialization ................................................................................................... 1220
18.4.2 Sample Sequencer Configuration ............................................................................... 1221
18.5 Register Map ............................................................................................................ 1221
18.6 Register Descriptions ................................................................................................. 1224
19 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 1309
19.1 Block Diagram ........................................................................................................... 1310
19.2 Signal Description ..................................................................................................... 1310
19.3 Functional Description ............................................................................................... 1312
19.3.1 Transmit/Receive Logic .............................................................................................. 1313
19.3.2 Baud-Rate Generation ............................................................................................... 1313
19.3.3 Data Transmission ..................................................................................................... 1314
19.3.4 Serial IR (SIR) ........................................................................................................... 1314
19.3.5 ISO 7816 Support ...................................................................................................... 1316
19.3.6 Modem Handshake Support ....................................................................................... 1316
19.3.7 9-Bit UART Mode ...................................................................................................... 1317
19.3.8 FIFO Operation ......................................................................................................... 1318
19.3.9 Interrupts .................................................................................................................. 1318
19.3.10 Loopback Operation .................................................................................................. 1319
19.3.11 DMA Operation ......................................................................................................... 1319
19.4 Initialization and Configuration .................................................................................... 1320
19.5 Register Map ............................................................................................................ 1321
19.6 Register Descriptions ................................................................................................. 1323
20 Quad Synchronous Serial Interface (QSSI) ..................................................... 1375
20.1 Block Diagram ........................................................................................................... 1375
20.2 Signal Description ..................................................................................................... 1376
20.3 Functional Description ............................................................................................... 1378
20.3.1 Bit Rate Generation ................................................................................................... 1378
20.3.2 FIFO Operation ......................................................................................................... 1378
20.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 1379
20.3.4 SSInFSS Function ..................................................................................................... 1380
20.3.5 High Speed Clock Operation ...................................................................................... 1381
20.3.6 Interrupts .................................................................................................................. 1381
20.3.7 Frame Formats ......................................................................................................... 1382
20.3.8 DMA Operation ......................................................................................................... 1389
20.4 Initialization and Configuration .................................................................................... 1389
20.4.1 Enhanced Mode Configuration ................................................................................... 1391
20.5 Register Map ............................................................................................................ 1391
20.6 Register Descriptions ................................................................................................. 1392
21 Inter-Integrated Circuit (I
2
C) Interface .............................................................. 1424
21.1 Block Diagram ........................................................................................................... 1425
21.2 Signal Description ..................................................................................................... 1426
21.3 Functional Description ............................................................................................... 1427
21.3.1 I
2
C Bus Functional Overview ...................................................................................... 1427
21.3.2 Available Speed Modes ............................................................................................. 1433
21.3.3 Interrupts .................................................................................................................. 1435
21.3.4 Loopback Operation .................................................................................................. 1436
21.3.5 FIFO and µDMA Operation ........................................................................................ 1436
21.3.6 Command Sequence Flow Charts .............................................................................. 1438
9December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller