Datasheet

Table 11-12. EPI General-Purpose Signal Connections (continued)
General- Purpose
Signal (D32)
General- Purpose
Signal (D24, A4)
General- Purpose
Signal (D16, A12)
General-Purpose
Signal (D8, A20)
EPI Signal
D21D21A5A13EPI0S21
D22D22A6A14EPI0S22
D23D23A7A15EPI0S23
D24A0
b
A8A16EPI0S24
D25A1A9A17EPI0S25
D26A2A10A18EPI0S26
D27A3A11A19EPI0S27
D28WRWRWREPI0S28
D29RDRDRDEPI0S29
D30FrameFrameFrameEPI0S30
D31ClockClockClockEPI0S31
a. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address.
b. In this mode, word accesses are used. AO is the LSB of the address and is equivalent to the system A2 address.
11.4.4.1 Bus Operation
A basic access is 1 EPI clock for write cycles and 2 EPI clocks for read cycles. An additional EPI
clock can be inserted into a write cycle by setting the WR2CYC bit in the EPIGPCFG register.
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0
Data
Clock
(EPI0S31)
Frame
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Address
Data
881December 13, 2013
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TM4C129XNCZAD Microcontroller