Datasheet

Each wait state adds 2 EPI clock cycles to the duration of the WRn or RDn strobe. During idle cycles,
the address and muxed address data signals maintain the state of the last cycle.
Figure 11-12 on page 876 shows a basic Host-Bus read cycle. Figure 11-13 on page 876 shows a
basic Host-Bus write cycle. Both of these figures show address and data signals in the
non-multiplexed mode (MODE field ix 0x1 in the EPIHBnCFG register).
Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0
Data
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
Address
Data
BSEL0n/
BSEL1n
a
a
BSEL0n and BSEL1n are available in Host-Bus 16 mode only.
Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0
Data
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
Address
Data
BSEL0n/
BSEL1n
a
a
BSEL0n and BSEL1n are available in Host-Bus 16 mode only.
Figure 11-14 on page 877 shows a write cycle with the address and data signals multiplexed (MODE
field is 0x0 in the EPIHBnCFG register). A read cycle would look similar, with the RDn strobe being
asserted along with CSn and data being latched on the rising edge of RDn.
December 13, 2013876
Texas Instruments-Advance Information
External Peripheral Interface (EPI)