Datasheet

Figure 11-8. PSRAM Burst Write
Latency (3 clocks)
DATA0 DATA1 DATA2
DATA3
EPICLK
EPI0S31
EPI0S[19:0]
ALE
CSn
OEn
EPI0S28
WRn
EPI0S29
iRDY
EPI0S32
EPI0S[15:0]
BSELn
ADDRESS
Note that if a read or write transfer attempts to begin during a refresh event, the transfer is held off
by the assertion of the iRDY pin by the memory to the EPI module. Figure 11-9 on page 872 and
Figure 11-10 on page 872 depict the delay in data transfer during a refresh collision.
871December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller