Datasheet

Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11
CLOCK
(EPI0S31)
IRDY
(EPI0S32)
State
Data A Data B Data C Data D Data E
IRDYDLY=11
IRDYDLY=01
IRDYDLY=10
Data F
Data A Data B Data C Data D Data E
Data A Data B Data C Data D Data E
Data A Data B Data C Data D Data E
Figure 11-6. iRDY Signal Connection
WAIT WAIT
Other
Device
Other
Device
IRDY
Cellular RAM
WAIT
Processor
11.4.3.2 PSRAM Support
The EPI Host Bus supports both a synchronous and asynchronous interface to PSRAM memory
when configured in 16-bit bus multiplexed mode. The EPIHBPSRAM register holds the values for
the PSRAM's bus configuration registers (CR). The contents of the EPIHBPSRAM register can be
sent to different memories depending on which WRCRE or RDCRE bit is set in the various
EPIHB16CFGn registers. For example, if the WRCRE bit is enabled in EPIHB16CFG, then the CRE
signal asserts and the contents are sent to the memory enabled by CS0. Enabling the WRCRE or
RDCRE bit in EPIHB16CFG2 register activates CS1n during a PSRAM configuration register write
or read. The WRCRE and RDCRE bit in EBIHB16CFG3 corresponds to CS2n and EPIHB16CFG4, to
CS3n. The WRCRE bit clears when the transfer is done. There must not be any system access or
non-blocking read activity during the CRE read or write-enable transfer. During a write to the PSRAM's
CR, the configuration data is written out on data pins [20:0] of the EPI bus. For a PSRAM configuration
read access, the RDCRE bit in the EPIHB16CFG register is set to signal that the next access is a
read of the PSRAM configuration register (CR). The address for the CR is written to bits CR[19:18]
of the EPIHBPSRAM register. The read data is returned at CR bits [15:0] of the EPIHBPSRAM
register.
Note: CRE read and write operations may only occur in asynchronous mode. During
synchronous mode the CRE bit should be disabled. Setting the CRE bit during
synchronous PSRAM accesses can lead to unpredictable behavior.
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December 13, 2013868
Texas Instruments-Advance Information
External Peripheral Interface (EPI)