Datasheet

Table 11-9. EPI Host-Bus 16 Signal Connections (continued)
HB16 Signal
(MODE
=XFIFO)
HB16 Signal (MODE
=ADNOMUX (Cont.
Read))
HB16 Signal (MODE
=ADMUX)
BSELCSCFGEPI Signal
-ALEALEX0x0
EPI0S30
CSnCSnCSnX0x1
CS0nCS0nCS0nX0x2
-ALEALEX0x3
-ALEALEX0x4
-CS0nCS0nX0x5
-ALEALEX0x6
Clock
d
Clock
d
Clock
d
XXEPI0S31
iRDYiRDYiRDYXXEPI0S32
XCS3nCS3nXXEPI0S33
XCS2nCS2nXXEPI0S34
XCRECREXXEPI0S35
a. "X" indicates the state of this field is a don't care.
b. In this mode, half-word accesses are used. A0 is the LSB of the address and is equivalent to the internal Cortex-M3 A1
address. This pin should be connected to A0 of 16-bit memories.
c. When an entry straddles several row, the signal configuration is the same for all rows.
d. The clock signal is not required for this mode.
The RDYEN in the EPIHBnCFG enables the monitoring of the external iRDY pin to stall accesses.
On the rising edge of EPI clock, if iRDY is low, access is stalled. The IRDYDLY can program the
number of EPI clock cycles in advance to the stall (1,2 or 3) as shown in Figure 11-5 on page 868.
This is a conceptual timing diagram of how the iRDY signal works with different IRDYDLY
configurations. When enabled, the iRDY stalls the EPI's internal states, while IRDYDLY controls the
delay pipeline when this stall takes affect. The iRDY signal can be connected to multiple devices
with a pull up resistor as shown in Figure 11-6 on page 868. Note that when multiple PSRAMs are
connected to iRDY, the EPIHPnCFG registers must be programmed to the same iRDY signal polarity
through the IRDYINV bit. When connected to a PSRAM, iRDY is used to control the address to
data latency.
867December 13, 2013
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