Datasheet

Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes (continued)
Addressable
Memory
Available
Address
Byte AccessBSELMax # of
External
Devices
CSCFGCSCFGEXTMODEHost Bus
Type
-noneNo020x300x3HB16
-noneYes120x300x3HB16
-noneNo010x010x3HB16
-noneYes110x010x3HB16
-noneNo040x110x3HB16
-noneYes140x110x3HB16
-noneNo040x210x3HB16
-noneYes140x210x3HB16
a. If byte selects are not used, data accesses are on 2-byte boundaries. As a result, the available address space is doubled.
b. Two EPI signals are used for byte selects, reducing the available address space by two bits.
Table 11-8 on page 862 shows how the EPI[31:0] signals function while in Host-Bus 8 mode.
Notice that the signal configuration changes based on the address/data mode selected by the MODE
field in the EPIHB8CFGn register and on the chip select configuration selected by the CSCFG and
CSCFGEXT field in the EPIHB8CFG2 register.
Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not
required and should be configured as a GPIO to reduce EMI in the system. Any unused EPI controller
signals can be used as GPIOs or another alternate function.
Table 11-8. EPI Host-Bus 8 Signal Connections
HB8 Signal (MODE
=XFIFO)
HB8 Signal (MODE
=ADNOMUX (Cont.
Read))
HB8 Signal (MODE
=ADMUX)
CSCFGEPI Signal
D0D0AD0X
a
EPI0S0
D1D1AD1XEPI0S1
D2D2AD2XEPI0S2
D3D3AD3XEPI0S3
D4D4AD4XEPI0S4
D5D5AD5XEPI0S5
D6D6AD6XEPI0S6
D7D7AD7XEPI0S7
-A0A8XEPI0S8
-A1A9XEPI0S9
-A2A10XEPI0S10
-A3A11XEPI0S11
-A4A12XEPI0S12
-A5A13XEPI0S13
-A6A14XEPI0S14
-A7A15XEPI0S15
-A8A16XEPI0S16
-A9A17XEPI0S17
-A10A18XEPI0S18
December 13, 2013862
Texas Instruments-Advance Information
External Peripheral Interface (EPI)