Datasheet

The MODE field of the EPIHBnCFGn registers configure the interface for the chip selects, which
support ADMUX or ADNOMUX. See Table 11-6 on page 860 for details on which configuration
register controls each chip select. If the CSBAUD bit is clear, all chip selects are configured by the
MODE bit field of the EPIHBnCFG register.
If the CSBAUD bit in the EPIHBnCFG2 register is set in Dual-chip select mode, the 2 chip selects
can use different clock frequencies, wait states and strobe polarity. If the CSBAUD bit is clear, both
chip selects use the clock frequency, wait states, and strobe polarity defined for CS0n. Additionally,
if the CSBAUD bit is set, the two chip selects can use different interface modes. If any interface modes
are programmed to ADMUX, then dual chip select mode must include the ALE capability. In quad
chip select mode, if the CSBAUD bit in the EPIHBnCFG2 register is set, the 4 chip selects can use
different clock frequencies, wait states and strobe polarity. If the CSBAUD bit is clear, all chip selects
use the clock frequency, wait states, and strobe polarity defined for CS0n. If the CSBAUD bit is set,
the four chip selects can use different interface modes.
Table 11-6. Chip Select Configuration Register Assignment
Corresponding Chip SelectConfiguration Register
a
CS0nEPIHBnCFG
CS1nEPIHBnCFG2
CS2nEPIHBnCFG3
CS3nEPIHBnCFG4
a. If the CSBAUD bit in the EPIHBnCFG2 register is clear and multiple chip selects are enabled, then all chip selects are
configured by the MODE bit field in the EPIHBnCFG register.
Note that multiple chip select modes do not allow the intermixing of Host-Bus 8 and Host-Bus16
modes.
When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data
can be read and written at any address, however these signals reduce the available address width
by 2 pins. The byte select signals are active Low. BSEL0n corresponds to the LSB of the halfword,
and BSEL1n corresponds to the MSB of the halfword.
When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes
at even addresses write invalid values into the odd byte. As a result, accesses should be made as
half-words (16-bits) or words (32-bits). In C/C++, programmers should use only short int and long
int for accesses. Also, because data accesses in HB16 mode with no byte selects are on 2-byte
boundaries, the available address space is doubled. For example, 28 bits of address accesses 512
MB in this mode. Table 11-7 on page 860 shows the capabilities of the HB8 and HB16 modes as
well as the available address bits with the possible combinations of these bits.
Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not
required and should be configured as a GPIO to reduce EMI in the system.
Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes
Addressable
Memory
Available
Address
Byte AccessBSELMax # of
External
Devices
CSCFGCSCFGEXTMODEHost Bus
Type
256 MB28 bitsAlwaysN/A10x0, 0x100x0HB8
128 MB27 bitsAlwaysN/A20x200x0HB8
64 MB26 bitsAlwaysN/A20x300x0HB8
128 MB27 bitsAlwaysN/A10x010x0HB8
128 MB27 bitsAlwaysN/A40x110x0HB8
December 13, 2013860
Texas Instruments-Advance Information
External Peripheral Interface (EPI)