Datasheet
If one of the Dual-Chip-Select modes is selected (CSCFGEXT is 0x0 and CSCFG is 0x2 or 0x3 in the
EPIHBnCFGn register), both chip selects can share the peripheral, code, or the memory space, or
one chip select can use the peripheral space and the other can use the memory or code space. In
the EPIADDRMAP register, if the EPADR field is not 0x0, the ECADR field is 0x0, and the ERADR
field is 0x0, then the address specified by EPADR is used for both chip selects, with CS0n being
asserted when the MSB of the address range is 0 and CS1n being asserted when the MSB of the
address range is 1. If the ERADR field is not 0x0, the ECADR field is 0x0, and the EPADR field is 0x0,
then the address specified by ERADR is used for both chip selects, with the MSB performing the
same delineation. If both the EPADR and the ERADR are not 0x0, and the ECADR field is 0x0 and the
EPI is configured for dual-chip selects, then CS0n is asserted for either address range defined by
EPADR and CS1n is asserted for either address range defined by ERADR. The two chip selects can
also be shared between the code space and memory or peripheral space. If the ECADR field is 0x1,
ERADR field is 0x0, and the EPADR field is not 0x0, then CS0n is asserted for the address range
defined by ECADR and CS1n is asserted for either address range defined by EPADR. If the ECADR
field is 0x1, EPADR field is 0x0, and the ERADR field is not 0x0, then CS0n is asserted for the address
range defined by ECADR and CS1n is asserted for either address range defined by ERADR.
In quad chip select mode (CSCFGEXT is 0x1 and CSCFG is 0x1 or 0x2 in the EPIHBnCFG2 register),
both the peripheral and the memory space must be enabled. In the EPIADDRMAP register, the
EPADR field is 0x3, the ERADR field is 0x3, and the ECADR field is 0x0. With this configuration, CS0n
asserts for the address range beginning at 0x6000.0000, CS1n asserts for 0x8000.0000, CS2n for
0xA000.0000, and CS3n for 0xC000.0000. Table 11-5 on page 859 gives a detailed explanation of
chip select address range mappings based on combinations of enabled peripheral and memory
space.
Note: Only one memory area can be mapped to a single chip select. Enabling multiple memory
areas for one chip select may produce unexpected results.
Table 11-5. Dual- and Quad- Chip Select Address Mappings
CS3CS2CS1CS0
a
ECADREPADRERADRChip Select
Mode
N/AN/AEPADR defined address
range (0xA000.000 or
0xC000.0000)
EPADR defined
address range
(0xA000.000 or
0xC000.0000)
0x00x1 or
0x2
0x0Dual-chip
select
N/AN/AERADR defined address
range (0x6000.000 or
0x8000.000)
ERADR defined
address range
(0x6000.000 or
0x8000.000)
0x00x00x1 or
0x2
Dual-chip
select
N/AN/AERADR defined address
range (0x6000.000 or
0x8000.000)
EPADR defined
address range
(0xA000.000 or
0xC000.0000)
0x00x1 or
0x2
0x1 or
0x2
Dual-chip
select
N/AN/AEPADR defined address
range (0xA000.0000 or
0xC000.0000)
ECADR defined
address range
(0x1000.000)
0x10x1 or
0x2
0x0Dual-chip
select
N/AN/AERADR defined address
range (0x6000.000 or
0x8000.000)
ECADR defined
address range
(0x1000.000)
0x10x00x1 or
0x2
Dual-chip
select
0xC000.00000xA000.00000x8000.00000x6000.00000x00x30x3Quad-chip
select
a. When CS0 & CS1 share address space, CS0 asserts when the MSB of the address is 0 and CS1, when the MSB of the
address is '1.'
859December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller