Datasheet

can be active High or Low by clearing or setting the ALEHIGH bit in the EPI Host-Bus n
Configuration (EPIHBnCFGn) register. CSn is best used for Host-Bus unmuxed mode in which
EPI address and data pins are separate. The CSn indicates when the address and data phases of
a read or write access are occurring. Both the ALE and the CSn modes can be enhanced to access
four external devices using settings in the EPIHBnCFGn register. PSRAM accesses must use both
ALE and CSn . Wait states can be added to the data phase of the access using the WRWS and RDWS
bits in the EPIHBnCFGn register. Additionally, within these wait state options, the WRWSM and RDWSM
bit of the EPIHBnTIMEn register can be set to reduce the given wait states by 1 EPI clock cycle for
finer granularity.
For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and
output to what the XFIFO can handle. FIFO mode is only applicable in EPI asynchronous mode.
Host-Bus 8 and Host-Bus 16 modes are very configurable. The user has the ability to connect 1,2,
or 4 external devices to the EPI signals, as well as control whether byte select signals are provided
in HB16 mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG
register, the CSCFG field and the CSCFGEXT bit in the EPIHBnCFGn register, and the BSEL bit in
the EPIHB16CFG register. The CSCFGEXT bit extends the chip select configuration possibilities by
providing the most significant bit of the CSCFG field. Refer to Table 11-4 on page 858 for the possible
ALE and chip select options that can be programmed by the combination of the CSCFGEXT and
CSCFG bits. Note that CSCFGEXT is the most significant bit.
Table 11-4. CSCFGEXT + CSCFG Encodings
DescriptionValue
ALE Configuration
EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the address and data
are muxed (MODE field in the EPIHB8CFG register is 0x0). The ALE signal is used by an external latch to
hold the address through the bus cycle.
0x0
CSn Configuration
EPI0S30 is used as a Chip Select (CSn). When using this mode, the address and data are generally not
muxed (MODE field in the EPIHB8CFG register is 0x1). However, if address and data muxing is needed,
the WR signal (EPI0S29) and the RD signal (EPI0S28) can be used to latch the address when CSn is low.
0x1
Dual CSn Configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined
by the most significant address bit for a respective external address map. This configuration can be used
for a RAM bank split between 2 devices as well as when using both an external RAM and an external
peripheral.
0x2
ALE with Dual CSn Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1n, and EPI0S26 is used as CS0n.
Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external
address map.
0x3
ALE with Single CSn Configuration
EPI0S30 is used as address latch (ALE) and EPI0S27 is used as CSn.
0x4
Quad CSn Configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33 is used
as CS3n.
0x5
ALE with Quad CSn Configuration
EPI0S30 is ALE, EPI0S26 is CS0n and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33
is used as CS3n.
0x6
Reserved0x7
December 13, 2013858
Texas Instruments-Advance Information
External Peripheral Interface (EPI)