Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

851

852

853

854

855

856

857

858

859

860

Figure 11-2. SDRAM Non-Blocking Read Cycle

Row Column Data 0 Data 1 ... Data n

CLK

(EPI0S31)

CKE

(EPI0S30)

CSn

(EPI0S29)

WEn

(EPI0S28)

RASn

(EPI0S19)

CASn

(EPI0S18)

DQMH, DQML

(EPI0S [17:16])

AD [15:0]

(EPI0S [15:0])

Activate NOP Read

NOP

Burst

Term

AD [15:0] driven in

AD [15:0] driven out AD [15:0] driven out

11.4.2.5 Normal Read Cycle

Figure 11-3 on page 856 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins

with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed

CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals follows

after 2 clock cycles. Following one more NOP cycle, data is read in on the EPI0S[15:0] signals

on every rising clock edge. The DQMH, DQML, and CSn signals are deasserted after the last

halfword of data is received, signaling the end of the cycle. At least one clock period of inactivity

separates any two SDRAM cycles.

Figure 11-3. SDRAM Normal Read Cycle

Row Column Data 0 Data 1

CLK