Datasheet

■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence or a μDMA transfer
■ Pin state can be retained during Hibernation mode; pins on port P can be programmed to wake
on level in Hibernation mode
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, 6-mA, 8-mA, 10-mA and 12-mA pad drive for digital communication; up to four
pads can sink 18-mA for high-current applications
– Slew rate control for 8-mA, 10-mA and 12-mA pad drive
– Open drain enables
– Digital input enables
1.3.9.8 LCD Controller (see page 1847)
The TM4C129XNCZAD controller integrates an LCD Controller which supports the following features:
■ Character-based panels
– Support for two character panels (CS0 and CS1) with independent and programmable bus
timing parameters when in asynchronous Hitachi, Motorola, and Intel modes
– Support for one character panel (CS0) with programmable bus timing parameters when in
synchronous Motorola and Intel modes
– Can be used as a generic 16-bit address/data interleaved MPU bus master with no external
stall
■ Passive matrix LCD panels
– Panel types including STN, DSTN, and C-DSTN
– AC Bias Control
■ Active matrix LCD panels
– Panel types including TN TFT
– 1, 2, 4, or 8 bits per pixel with palette RAM and 16 or 24 bits per pixel without palette RAM
■ OLED Panels
– Passive Matrix (PM OLED) with frame buffer and controller IC inside the panel
– Active Matrix (AM OLED)
■ Bus mastering capability from either system SRAM or EPI memory.
December 13, 201382
Texas Instruments-Advance Information
Architectural Overview