Datasheet

The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific

peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the

GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by

default. When a bit is set in the GPIOAFSEL register, the corresponding GPIO signal is controlled

by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions

for each GPIO, providing additional flexibility in signal definition. For information on the defined

encodings for the bit fields in this register, refer to Table 31-5 on page 2087. The reset value for this

Note: If a particular input signal to a peripheral is assigned to two different GPIO port pins, the

signal is assigned to the port with the lowest letter and the assignment to the higher letter

port is ignored. If a particular output signal from a peripheral is assigned to two different

GPIO port pins, the signal will output to both pins. Assigning an output signal from a

peripheral to two different GPIO pins is not recommended.

Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,

GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0), with the exception of

the pins shown in the table below. A Power-On-Reset (POR) puts the pins back to their

default state.

Table 10-12. GPIO Pins With Non-Zero Reset Values

GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault StateGPIO Pins

0x11011JTAG/SWDPC[3:0]

The GPIO commit control registers provide a layer of protection against accidental

programming of critical hardware signals including the GPIO pins that can function as

JTAG/SWD signals and the NMI signal. The commit control process must be followed

for these pins, even if they are programmed as alternate functions other than JTAG/SWD

or NMI; see “Commit Control” on page 783.

Note: If the device fails initialization during reset, the hardware toggles the TDO output

as an indication of failure. Thus, during board layout, designers should not

designate the TDO pin as a GPIO in sensitive applications where the possibility

of toggling could affect the design.

December 13, 2013818

Texas Instruments-Advance Information

General-Purpose Input/Outputs (GPIOs)