Datasheet

Note: Pins configured as digital inputs are Schmitt-triggered.

The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed

below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do

not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To

use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIODEN

bit must be set.

Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,

GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0), with the exception of

the pins shown in the table below. A Power-On-Reset (POR) puts the pins back to their

default state.

Table 10-11. GPIO Pins With Non-Zero Reset Values

GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault StateGPIO Pins

0x11011JTAG/SWDPC[3:0]

The GPIO commit control registers provide a layer of protection against accidental

programming of critical hardware signals including the GPIO pins that can function as

JTAG/SWD signals and the NMI signal. The commit control process must be followed

for these pins, even if they are programmed as alternate functions other than JTAG/SWD

or NMI; see “Commit Control” on page 783.

Note: If the device fails initialization during reset, the hardware toggles the TDO output

as an indication of failure. Thus, during board layout, designers should not

designate the TDO pin as a GPIO in sensitive applications where the possibility

of toggling could affect the design.

Note: The GPIO commit control registers provide a layer of protection against accidental

programming of critical hardware peripherals. Protection is provided for the GPIO pins that

can be used as the four JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 2034

for pin numbers). Writes to protected bits of the GPIO Alternate Function Select

(GPIOAFSEL) register (see page 801), GPIO Pull Up Select (GPIOPUR) register (see

page 807), GPIO Pull-Down Select (GPIOPDR) register (see page 809), and GPIO Digital

Enable (GPIODEN) register (see page 812) are not committed to storage unless the GPIO

Lock (GPIOLOCK) register (see page 814) has been unlocked and the appropriate bits of

the GPIO Commit (GPIOCR) register (see page 815) have been set.

December 13, 2013812

Texas Instruments-Advance Information

General-Purpose Input/Outputs (GPIOs)